9.3.4 GATE

This pin provides gate drive to the internal MOSFET. A charge pump sources 30 µA to enhance the internal MOSFET. A 13.9 V clamp between GATE and VCC limits the gate-to-source voltage since V_VCC is close to V_OUT in normal operation. During start up, a transconductance amplifier regulates the gate voltage of the internal FET to provide inrush current limiting. The TIMER pin charges timer capacitor C_T during the inrush. Inrush current limiting continues until the V_{(GATE – VCC)} exceeds the Timer Activation Voltage 5.8 V for V_VCC = 12 V. Then the TPS2475x enters into circuit breaker mode. In the circuit breaker mode, the current flowing in R_SENSE is compared with the current limit threshold derived from the MOSFET power limit scheme (see the PROG definition). If the current flowing in R_SENSE exceeds the current limit threshold, then the internal pass MOSFET will be turned off. The GATE pin is disabled by the following three mechanisms:

1. GATE is pulled down by an 11-mA current source when
   • The fault timer expires during an overload current fault (V_IMON > 675 mV)
   • V_EN is below its falling threshold
   • V_VCC drops below the UVLO threshold
   • V_OV is above its rising threshold
2. GATE is pulled down by a 1-A current source for 13.5 µs when a hard output short circuit occurs and V_{(VCC – SENSE)} is greater than 60 mV, that is, the fast-trip shutdown threshold. After fast-trip shutdown is complete, an 11-mA sustaining current ensures that the internal FET remains off.
3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising threshold.

GATE remains low in latch mode (TPS24750) and attempts a restart periodically in retry mode (TPS24751).

Connect a capacitor from this pin to GND to control the slew rate of the output voltage at power-on. This pin can be left floating to obtain a predetermined slew rate on the output.

If used, any capacitor connecting GATE and GND must not exceed 1 μF and it must be connected in series with a resistor of no less than 1 kΩ. No external resistor must be directly connected from GATE to GND or from GATE to OUT.