9.4.7.2 Start-Up of Hot-Swap Circuit by VCC or EN

The connection and disconnection between a load and the input power bus are controlled by turning on and turning off the internal FET.

The TPS2475x has two ways to turnon the internal FET:

• Increasing V_VCC above UVLO upper threshold while EN is already higher than its upper threshold sources current to the gate of internal FET. After an inrush period, the TPS2475x fully turns on internal FET.
• Increasing EN above its upper threshold while V_VCC is already higher than the UVLO upper threshold sources current to the gate of internal FET. After an inrush period, the TPS2475x fully turns on internal FET.

The EN pin can be used to start up the TPS2475x at a selected input voltage V_VCC.

To isolate the load from the input power bus, the internal FET can be disabled by any of the following conditions: UVLO, EN, load current above the current-limit threshold, hard short at load, OV, or OTSD. Three separate mechanisms disable the internal FET by pulling down the GATE as described below:

1. GATE is pulled down by an 11-mA current source when any of the following occurs.
   • The fault timer expires during an overload current fault (V_IMON > 675 mV).
   • V_EN is below its falling threshold.
   • V_VCC drops below the UVLO threshold.
   • V_OV is above its rising threshold.
2. GATE is pulled down by a 1-A current source for 13.5 μs when a hard output short circuit occurs and V_{(VCC – SENSE)} is greater than 60 mV, that is, the fast-trip shutdown threshold. After fast-trip shutdown is complete, an 11-mA sustaining current ensures that the internal FET remains off.
3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising threshold.