ZHCSNB6A April 2021 – February 2022 TPS23882B
PRODUCTION DATA
COMMAND = 17h with 1 Data Byte, Read/Write
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INTEN | – | nbitACC | MbitPrty | CLCHE | DECHE | – | – |
| R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | INTEN | R/W | 1 | INT pin mask bit. Writing a 0 will mask any bit of Interrupt register from activating the INT output, whatever the state of the Interrupt Mask register. Note that activating INTEN has no impact on the event registers. 1 = Any unmasked bit of Interrupt register can activate the INT output 0 = INT output cannot be activated |
| 6 | – | R/W | 0 | |
| 5 | nbitACC | R/W | 0 | I2C Register Access Configuration bit. 1 = Configuration B. This means 16-bit access with a single device address (A0 = 0). 0 = Configuration A. This means 8-bit access, while the 8-channel device is treated as 2 separate 4-channel devices with 2 consecutive target addresses. See register 0x11 for more information on the I2C address programming |
| 4 | MbitPrty | R/W | 0 | Multi Bit Priority bit. Used to select between 1-bit shutdown priority and 3-bit shutdown priority. 1 = 3-bit shutdown priority. Register 0x27 and 0x28 need to be followed for priority and OSS action. 0 = 1-bit shutdown priority. Register 0x15 needs to be followed for priority and OSS action |
| 3 | CLCHE | R/W | 0 | Class change Enable bit. When set, the CLSCn bits in Detection Event register only indicates when the result of the most current classification operation differs from the result of the previous one. 1 = CLSCn bit is set only when a change of class occurred for the associated channel. 0 = CLSCn bit is set each time a classification cycle occurred for the associated channel. |
| 2 | DECHE | R/W | 0 | Detect Change Enable bit. When set, the DETCn bits in Detection Event register only indicates when the result of the most current detection operation differs from the result of the previous one. 1 = DETCn bit is set only when a change in detection occurred for the associated channel. 0 = DETCn bit is set each time a detection cycle occurred for the associated channel. |
| 1 | – | R/W | 0 | |
| 0 | – | R/W | 0 |
If the MbitPrty bit needs to be changed from 0 to 1, make sure the OSS input pin is in the idle (low) state for a minimum of 200 μsec prior to setting the MbitPrty bit, to avoid any misbehavior related to loss of synchronization with the OSS bit stream.
Only the nbitACC bit for channels 1-4 needs to be set to enable 16-bit I2C operation.
| Cmd Code | Register or Command Name | Bits Description | Configuration A (8-bit) | Configuration B (16-bit) |
|---|---|---|---|---|
| 00h | INTERRUPT | INT bits P1-4, P5-8 | Separate mask and interrupt result per group of 4 channels. The Supply event bit is repeated twice. | |
| 01h | INTERRUPT MASK | MSK bits P1-4, P5-8 | ||
| 02h | POWER EVENT | PGC_PEC P4-1, P8-5 | Separate event byte per group of 4 channels. | |
| 03h | ||||
| 04h | DETECTION EVENT | CLS_DET P4-1, P8-5 | ||
| 05h | ||||
| 06h | FAULT EVENT | DIS_PCUT P4-1, P8-5 | ||
| 07h | ||||
| 08h | START/ILIM EVENT | ILIM_STR P4-1, P8-5 | ||
| 09h | ||||
| 0Ah | SUPPLY/FAULT EVENT | TSD, VDUV, VDUW, VPUV , RAMFLT OSSE4-1, OSSE8-5 | Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same results for TSD, VDUV, VPUV and RAMFLT. The PCUTxx and OSSEx bits will. have separate status per group of 4 channels. Clearing at least one VPUV/VDUV also clears the other one. | |
| 0Bh | ||||
| 0Ch | CHANNEL 1 DISCOVERY | CLS&DET1_CLS&DET5 | Separate Status byte per channel | |
| 0Dh | CHANNEL 2 DISCOVERY | CLS&DET2_CLS&DET6 | ||
| 0Eh | CHANNEL 3 DISCOVERY | CLS&DET3_CLS&DET7 | ||
| 0Fh | CHANNEL 4 DISCOVERY | CLS&DET4_CLS&DET8 | ||
| 10h | POWER STATUS | PG_PE P4-1, P8-5 | Separate status byte per group of 4 channels | |
| 11h | PIN STATUS | A4-A1,A0 | Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same result, except that A0 = 0 (channel 1 to 4) or 1 (channel 5 to 8). | Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same result, including A0 = 0. |
| 12h | OPERATING MODE | MODE P4-1, P8-5 | Separate Mode byte per group of 4 channels. | |
| 13h | DISCONNECT ENABLE | DCDE P4-1, P8-5 | Separate DC disconnect enable byte per group of 4 channels. | |
| 14h | DETECT/CLASS ENABLE | CLE_DETE P4-1, P8-5 | Separate Detect/Class Enable byte per group of 4 channels. | |
| 15h | PWRPR/2P-PCUT DISABLE | OSS_DCUT P4-1, P8-5 | Separate OSS/DCUT byte per group of 4 channels. | |
| 16h | TIMING CONFIG | TLIM_TSTRT_TOVLD_TMPDO P4-1, P8-5 | Separate Timing byte per group of 4 channels. | |
| 17h | GENERAL MASK | P4-1, P8-5 including n-bit access | Separate byte per group of 4 channels. n-bit access: Setting this in at least one of the virtual quad register space is enough to enter Config B mode. To go back to config A, clear both. MbitPrty: Setting this in at least one of the virtual quad register space is enough to enter 3-bit shutdown priority. To go back to 1-bit shutdown, clear both MbitPrty bits. | |
| 18h | DETECT/CLASS Restart | RCL_RDET P4-1, P8-5 | Separate DET/CL RST byte per group of 4 channels | |
| 19h | POWER ENABLE | POF_PWON P4-1, P8-5 | Separate POF/PWON byte per group of 4 channels | |
| 1Ah | RESET | P4-1, P8-5 | Separate byte per group of 4 channels, Clear Int pin and Clear All int. | Separate byte per group of 4 channels. |
| 1Bh | ID | Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same result unless modified through I2C. | ||
| 1Ch | AUTOCLASS | AC4-1, AC8-5 | Separate byte per group of 4 channels. | |
| 1Eh | 2P POLICE 1/5 CONFIG | POL1, POL5 | Separate Policing byte per channel. | |
| 1Fh | 2P POLICE 2/6 CONFIG | POL2, POL6 | ||
| 20h | 2P POLICE 3/7 CONFIG | POL3, POL7 | ||
| 21h | 2P POLICE 4/8 CONFIG | POL4, POL8 | ||
| 22h | CAP MEASUREMENT | CDET4-1, CDET8-5 | Separate capacitance measurement enable bytes per group of 4 channels. | |
| 24h | Power-on FAULT | PF P4-1, P8-5 | Separate Power-on FAULT byte per group of 4 channels | |
| 25h | ||||
| 26h | PORT REMAPPING | Logical P4-1, P8-5 | Separate Remapping byte per group of 4 channels. Reinitialized only if POR or RESET pin. Kept unchanged if 0x1A IC reset or CPU watchdog reset. | |
| 27h | Multi-Bit Priority 21 / 65 | MBP2-1, MBP6-5 | Separate MBP byte per group of 2 channels | |
| 28h | Multi-Bit Priority 43 / 87 | MBP4-3, MBP8-7 | Separate MBP byte per group of 2 channels | |
| 29h | PORT POWER ALLOCATION | MC34-12, MC78-56 | Separate MCnn byte per group of 4 channels | |
| 2Ch | TEMPERATURE | TEMP P1-4, P5-8 | Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same result. | |
| 2Eh | INPUT VOLTAGE | VPWR P1-4, P5-8 | Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same result. | |
| 2Fh | ||||
| 30h | CHANNEL 1 CURRENT | I1, I5 | Separate 2-byte per group of 4 channels | Separate 2-byte per group of 4 channels. 2-byte Read at 0x30 gives I1 4-byte Read at 0x30 gives I1, I5. |
| 31h | N/A | 2-byte Read at 0x31 gives I5. | ||
| 32h | CHANNEL 1 VOLTAGE | V1, V5 | Separate 2-byte per group of 4 channels | 2-byte Read at 0x32 gives V1 4-byte Read at 0x32 gives V1, V5. |
| 33h | N/A | 2-byte Read at 0x33 gives V5. | ||
| 34h | CHANNEL 2 CURRENT | I2, I6 | Separate 2-byte per group of 4 channels | 2-byte Read at 0x34 gives I2 4-byte Read at 0x34 gives I2, I6. |
| 35h | N/A | 2-byte Read at 0x35 gives I6. | ||
| 36h | CHANNEL 2 VOLTAGE | V2, V6 | Separate 2-byte per group of 4 channels | 2-byte Read at 0x36 gives V2 4-byte Read at 0x36 gives V2, V6. |
| 37h | N/A | 2-byte Read at 0x37 gives V6. | ||
| 38h | CHANNEL 3 CURRENT | I3, I7 | Separate 2-byte per group of 4 channels | 2-byte Read at 0x38 gives I3 4-byte Read at 0x38 gives I3, I7. |
| 39h | N/A | 2-byte Read at 0x39 gives I7. | ||
| 3Ah | CHANNEL 3 VOLTAGE | V3, V7 | Separate 2-byte per group of 4 channels | 2-byte Read at 0x3A gives V3 4-byte Read at 0x3A gives V3, V7. |
| 3Bh | N/A | 2-byte Read at 0x3B gives V7. | ||
| 3Ch | CHANNEL 4 CURRENT | I4, I8 | Separate 2-byte per group of 4 channels | 2-byte Read at 0x3C gives I4 4-byte Read at 0x3C gives I4, I8. |
| 3Dh | N/A | 2-byte Read at 0x3D gives I8. | ||
| 3Eh | CHANNEL 4 VOLTAGE | V4, V8 | Separate 2-byte per group of 4 channels | 2-byte Read at 0x3E gives V4 4-byte Read at 0x3E gives V4, V8. |
| 3Fh | N/A | 2-byte Read at 0x3F gives V8. | ||
| 40h | OPERATIONAL FOLDBACK | 2xFB4-1, 2xFB8-5 | Separate 2xFBn config byte per group of 4 channels. | |
| 41h | FIRMWARE REVISION | FRV P1-4, P5-8 | Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same result. | |
| 42h | I2C WATCHDOG | P1-4, P5-8 | IWD3-0: if at least one of the two 4-port settings is different than 1011b, the watchdog is enabled for all 8 channels. WDS: Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same WDS result. Each WDS bit needs to be cleared individually through I2C. | |
| 43h | DEVICE ID | DID_SR P1-4, P5-8 | Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same result . | |
| 44h | CHANNEL 1 RESISTANCE | RDET1, RDET5 | Separate byte per channel. Detection resistance always updated, detection good or bad. | |
| 45h | CHANNEL 2 RESISTANCE | RDET2, RDET6 | ||
| 46h | CHANNEL 3 RESISTANCE | RDET3, RDET7 | ||
| 47h | CHANNEL 4 RESISTANCE | RDET4, RDET8 | ||
| 4Ch | CHANNEL 1 ASSIGNED CLASS | ACLS&PCLS1_ACLS&PCLS5 | Separate Status byte per channel | |
| 4Dh | CHANNEL 2 ASSIGNED CLASS | ACLS&PCLS2_ACLS&PCLS6 | ||
| 4Eh | CHANNEL 3 ASSIGNED CLASS | ACLS&PCLS3_ACLS&PCLS7 | ||
| 4Fh | CHANNEL 4 ASSIGNED CLASS | ACLS&PCLS4_ACLS&PCLS8 | ||
| 50h | AUTOCLASS CONTROL | MAC4-1, AAC4-1, MAC8-5, AAC8-5 | Separate Auto Class control bytes per 4 channels | |
| 51h | AUTOCLASS POWER 1/5 | PAC1, PAC5 | Separate Auto Class Power Measurement byte per channel | |
| 52h | AUTOCLASS POWER 2/6 | PAC2, PAC6 | ||
| 53h | AUTOCLASS POWER 3/7 | PAC3, PAC7 | ||
| 54h | AUTOCLASS POWER 4/8 | PAC4, PAC8 | ||
| 55h | ALTERNATIVE FOLDBACK | ALTFB4-1, ALTIR4-1, ALTFN8-5, ALTIR8-5 | Separate Alternative Foldback byte per group of 4 channels | |
| 60h | SRAM CONTROL | SRAM CNTRL BITS | These bits must be configured for the lower virtual quad (A0=0, CH 1-4)). These bits have no functionality for the upper virtual quad (A0=1, Ch 5-8) device | |
| 61h | SRAM DATA | Streaming data input is independent of I2C configuration | ||
| 62h | START ADDRESS (LSB) | These bits must be configured for the lower virtual quad (A0=0, CH 1-4)). These bits have no functionality for the upper virtual quad (A0=1, Ch 5-8) device | ||
| 63h | START ADDRESS (MSB) | These bits must be configured for the lower virtual quad (A0=0, CH 1-4)). These bits have no functionality for the upper virtual quad (A0=1, Ch 5-8) device | ||