ZHCSNB6A April 2021 – February 2022 TPS23882B
PRODUCTION DATA
The TPS23882B is configured with internal SRAM memory fault monitoring, and in the event that an error is detected with the SRAM memory, the device will enter “safe mode”. While in “Safe mode” the FW Revision value in register 0x41 will be set to 0xFFh.
Any channels that are currently powered will remain powered, but the majority of the operation will be disabled until the SRAM can be reloaded. The device UVLO and Thermal Shutdown features in addition to the disconnect and current foldback functions for the powered channels will be preserved in “safe mode”.
Any channels that were not powered prior to the SRAM fault detection will be set to OFF mode (see register 0x12h description for additional changes that will occur as a result of the change to OFF mode). Port Remapping (0x26h) and any other channel configuration settings (ie Power Allocation 0x29h) will be preserved.
Upon detection of a SRAM fault the “RAM_EN” bit in 0x60 will be cleared and the RAMFLT bit will be set in register 0x0A. The internal firmware will continue to run in “safe mode” until this bit is set again by the host after the SRAM is reloaded or a POR (Power on Reset) event occurs. In order to ensure a smooth transition into and out of “safe mode”, any I2C commands other than those to reprogram the SRAM need to be deferred until after the SRAM is reloaded and determined to be “valid” (see register 0x60 SRAM programing descriptions).
Once set, the RAMFLT bit will remain set even after the device is removed from safe mode. it is recommend that this bit be cleared prior to setting the RAM_EN bit in register 0x60 following the SRAM reload.
The PAR_EN bit in reg 0x60 must be set and the corresponding SRAM_Parity code (available for download from the TI mySecure Software webpage) must be loaded into the device in order for the SRAM fault monitoring to be active.
Please refer to the How to Load TPS2388x SRAM Code document for more information on the recommended SRAM programming procedure.