ZHCSNE6 August 2021 TPS1653
PRODUCTION DATA
The EN pin can be used to turn-on or turn-off the internal FET. EN can be used with a 1.8-V Digital IO of FPGA or MCU. For rising and falling thresholds of EN pin. See VENR and VENF in Electrical Characteristics. After the EN is made low, the output ramps with slew rate configured by dVdT pin.
EN pin does not reset the latch in latch mode (MODE = Open) and making EN pin high asserts the FLT pin. See the Parameter Measurement Information for the behavior of FLT with EN pin.