2 修訂歷史記錄
Changes from September 1, 2012 to April 24, 2015 (from A Revision () to B Revision)
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刪除了Figure 1-1 中的安全/密鑰管理器Go
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Removed "Secure ROM Boot" and changed "Public ROM Boot" to "ROM Boot" in Section 3.5Go
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Added Boot Parameter Table sectionGo
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Updated OUTPUT_DIVIDE default value and PLL clock formula in PLL Settings sectionGo
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Clarified SmartReflex pin output typeGo
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Added DDR3PLLCTL1 register to Device Status Control Registers tableGo
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Revised IPCGRH register de0scriptionGo
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Corrected SmartReflex peripheral I/O Buffer Type from LVCMOS category to Open drainGo
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Updated ”slow peripherals” in SYSCLK7 description Go
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Updated BWADJ value setting description in Main/DDR3 PLL contol registersGo
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Updated all SerDes clocks to discrete frequencies in the Clock Input Timing Requirements tableGo
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Corrected differential clock rise and fall time in the PLL timing table for the clock inputs that feed into the LJCB clock buffersGo
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Added note to DDR3 PLL initialization sequenceGo
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Clarified table caption and first column headingGo
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Corrected MPU0 Memory Protection End Address from 0x026203FF to 0x026207FFGo
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Removed SECURITY LEVEL column from Table 8-43Go
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Updated/Changed Bit 7 of Table 8-53 from "NS" to "Reserved"Go
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Added MPU Registers Reset Values sectionGo
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Updated the Min/Max values of EMIF read cycle time and write cycle timeGo
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Updated Timer number description across the data manualGo
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Changed all footnote references from CORECLK to SYSCLK1Go
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Updated the descriptions of how Semaphore module is accessibleGo
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Corrected McBSP FIFO Control and Status Register address to be 0x021B6000 for McBSP0 and 0x021BA000 for McBSP1Go
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Corrected McBSP FIFO Data Register address to be 0x22400000 for McBSP1Go
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Updated Trace Electrical Timing tables and Timing diagramsGo
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Removed SECURITY information from Figure 9-1Go