ZHCSCV4C October 2014 – April 2021 TMP451-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Map
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
6.6 Timing Characteristics for Figure 6-1
| PARAMETER | FAST MODE | HIGH-SPEED MODE | UNIT | ||||
|---|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | ||||
| ?(SCL) | SCL operating frequency | 0.001 | 0.4 | 0.001 | 2.5 | MHz | |
| t(BUF) | Bus free time between STOP and START Condition | 1300 | 260 | ns | |||
| t(HDSTA) | Hold time after repeated START condition. After this period, the first clock is generated. | 600 | 160 | ns | |||
| t(SUSTA) | Repeated START condition setup time | 600 | 160 | ns | |||
| t(SUSTO) | STOP condition setup time | 600 | 160 | ns | |||
| t(HDDAT) | Data hold time | 0 | 900 | 0 | 150 | ns | |
| t(SUDAT) | Data setup time | 100 | 30 | ns | |||
| t(LOW) | SCL clock LOW period | 1300 | 260 | ns | |||
| t(HIGH) | SCL clock HIGH period | 600 | 60 | ns | |||
| tF, tR – SDA | Data fall and rise time | 300 | 80 | ns | |||
| tF, tR – SCL | Clock fall and rise time | 300 | 40 | ns | |||
| tR | Rise time for SCL ≤ 100 kHz | 1000 | ns | ||||
Figure 6-1 Two-Wire Timing Diagram