8.3.1 Reset Implementation

When OE is de-asserted, control signal inputs are ignored; the HDMI inputs and outputs are high impedance. It is critical to transition the OE from a low level to high after the V_CC supply has reached the minimum recommended operating voltage. This is achieved by a control signal to the OE input, or by an external capacitor connected between OE and GND. To insure the TMDS171 is properly reset, the OE pin must be de-asserted for at least 100 μs before being asserted. When OE is re-asserted the TMDS171 will have to be reprogrammed if it was programmed by I²C and not pin strapping. When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of the V_CC supply, where a slower ramp-up results in a larger value external capacitor. Refer to the latest reference schematic for TMDS171; consider approximately 200 nF capacitor as a reasonable first estimate for the size of the external capacitor. Both OE implementations are shown in Figure 21 and Figure 22.

Figure 21. External Capacitor Controlled OE

Figure 22. OE Input from Active controller

8.3.2 Operation Timing

TMDS171 starts to operate after the OE signal is properly set after power up timing complete. See Figure 23, Figure 24, Table 1. If OE is held low until V_DD and V_CC become stable there is no rail sequence requirement.

Figure 23. Power up Timing for TMDS171

Figure 24. CDR Timing for TMDS171

8.3.3 Swap and Polarity Working (Retimer Mode Only)

TMDS171 incorporates swap function which can set the input lanes in swap mode. The IN_D2 will route to the OUT_CLK position by swapping with IN_CLK. The IN_D1 swaps with IN_D0. The Swap function only changes the input pins. The EQ setup follows the new mapping, see Figure 25. This function can be used with the SWAP/POL pin 1 and control the register 0x09h bit 7 for SWAP enable. The Swap function works in both redriver and retimer mode. The TMDS171 can also swap the input polarity signals. When SWAP/POL is high the n and p pins on each lane will swap. Polarity swap only works when in retimer mode. When this function is enabled and the device is in automatic cross over mode between redriver and retimer modes, care must be taken to avoid losing polarity swap. When the data rate drops to the redriver level, the polarity swap is lost.

Figure 25. TMDS171 Swap Function

8.3.4 TMDS Inputs

Standard TMDS terminations are integrated on all TMDS inputs. External terminations are not required. Each input data channel contains an adaptive or fixed equalizer to compensate for Inter-Symbol Interference (ISI) due to cable, connector, and/or board trace losses. The voltage at the TMDS input pins must be limited under the absolute maximum ratings. TMDS input pins have incorporated failsafe circuits. An unused input channel can be externally biased to prevent output oscillation by connecting the N input pin to be grounded through a 1-kΩ resistor and the other pin left open. The input pins can be polarity changed through local I²C register when in retimer mode.

8.3.5 TMDS Inputs Debug Tools

There are two methods for debugging a system to make sure the inputs to the TMDS171 are valid. A TMDS error checker is implemented to provide a rough Bit Error Rate per data lane. This allows the system implementer to determine how the link between the source and TMDS171 is performing on all three data lanes. See CSR BIT FIELD DEFINITIONS – RX PATTERN VERIFIER CONTROL/STATUS register.

If a high error count is evident the TMDS171 has a way to view the general receiver eye quality. A tool is available that uses the I²C link to down load the data that can be plotted for an eye diagram. This is available per data lane. This tool also provides a method to turn on an internal PRBS generator that will transmit a data signal on the data pins. A clock at the proper frequency is required on the IN_CLK pins to generated the expected output data rate.

8.3.6 Receiver Equalizer

The equalizer used to clean up inter-symbol interference (ISI) jitter/loss from the bandwidth-limited board traces or cables. TMDS171 supports fixed receiver equalizer and adaptive equalizer by setting the EQ_SEL/A0 pin or through I²C. When EQ_SEL/A0 is high, the EQ gain is fixed to 10 dB and when set low the EQ gain is set to 7.5 dB. TMDS171 operates in adaptive equalizer mode when EQ_SEL/A0 pin is left floating. The EQ gain will be automatically adjusted based on the data rate to compensate for trace or cable loss. Implementers can enable the various EQ settings through local I²C control.

Figure 26. Adaptive EQ Gain Curve

8.3.7 Input Signal Detect Block

When SIG_EN is enabled, the TMDS looks for a valid TMDS clock signal input. The terminations on the TMDS data lines are connected and the device is fully functional when a valid signal is detected. If no valid TMDS clock signal is detected, the device enters standby mode waiting for a valid signal at the clock input. The internal CDR is shut down and all of the TMDS outputs are in high-Z status. TMDS signal detect circuit can be set as enable by SIG_EN pin or through local I²C control but is default disabled. Designers are recommended to activate this function in normal operation for power saving.

8.3.8 Audio Return Channel

The Audio Return Channel in TMDS171 enables a TV, via a single HDMI cable, to send audio data “upstream” to an A/V receiver or surround audio controller, increasing user flexibility and eliminating the need for any separate S/PDIF audio connection. The TMDS171 supports single mode audio return channel. Implementers can send the S/PDIF signal to SPDIF_IN. The signal from ARC_OUT is sent to HDMI connectors and is passed through the general HDMI cable to audio receiver. By I²C control, customer can disable ARC_OUT by register. Enabled by default after initialization.

8.3.9 Transmitter Impedance Control

Source termination is disabled at data rates < 2 Gbps. When the data rate is between 2 Gbps and 3.4 Gbps, the output signal may be better if the termination value around 150 Ω to 300 Ω depending upon system implementation. TMDS171 supports two different source termination impedances for ease of implementation. Pin 36, TX_TERM_CTL, offers a selection option to choose the output termination impedance value.

8.3.10 TMDS Outputs

A 1% precision resistor, 7.06 kΩ, connected from VSADJ to ground is recommended to allow the differential output swing to comply with TMDS signal levels. The differential output driver provides a typical 10 mA current sink capability, which provides a typical 500 mV voltage drop across a 50 Ω termination resistor.

Figure 27. TMDS Driver and Termination Circuit

In Figure 27, if V_CC (TMDS171 supply) and AVCC (sink termination supply) are both powered, the TMDS output signals are high impedance when OE = high. Both supplies being active are the normal operating condition. Again refer to Figure 27, if V_CC is on and AVCC is off, the TMDS outputs source a typical 5 mA current through each termination resistor to ground. A total of 33 mW of power is consumed by the terminations independent of the OEB logical selection. When AVCC is powered on, normal operation (OE controls output impedance) is resumed. When the power source of the device is off and the power source to termination is on, the IO(off), output leakage current, specification ensures the leakage current is limited to 45 μA or less. The PRE_SEL pin provides – 2 dB de-emphasis gain, allowing output signal pre-conditioning to offset interconnect losses from the TMDS171 outputs to a TMDS receiver. De-emphasis is recommended to be set at 0 dB while connecting to a receiver through short PCB route. The V_OD of the data lanes and clock lane can be adjusted through I²C. See Table 11 for detail. Figure 1 shows the different output voltages based on the different VSADJ settings.

8.3.11 Pre-Emphasis/De-Emphasis

The TMDS171 provides de-emphasis as a way to compensate for ISI loss between the TMDS171 outputs and a TMDS receiver. There are two methods to implement this function. When in pin strapping mode the PRE_SEL pin controls this function. The PRE_SEL pin provides - 2 dB or 0 dB de-emphasis, which allows the output signal pre-conditioning. De-emphasis is recommended to be set at 0-dB while connecting to a receiver through short PCB traces. When pulled to ground through a 65 kΩ resistor - 2 dB can be realized, see Figure 9. When using I²C, reg0Ch[1:0] is used to make these adjustments.

As there are times that true pre-emphasis may be the best solution there are two methods to accomplish this. If pin strapping is being used the best method is to reduce the VSADJ resistor value thus increasing the V_OD swing and then pulling the PRE_SEL pin to ground using a 65 kΩ resistor, see Figure 28. If using I²C there are two methods to accomplish this. The first is similar to pin strapping but reducing VSADJ resistor value and then implementing - 2 db de-emphasis through I²C, reg0Ch[1:0] = 01. The second method is to increase the VOD swing by setting reg0Ch[7:5] = 011 and reg0Ch[1:0] = 01 which will accomplish the same pre-emphasis value, see Figure 29. Note: De-emphasis is only implement able during retimer mode. In redriver mode this function is not available.

Figure 28. Pre-emphasis Using Pin Strapping

Figure 29. Pre-emphasis Using I²C

8.4.1 Retimer Mode

Clock and Data Recovery Circuits (CDR) are used to track, sample and retime the equalized data bit streams. The CDRs are designed with loop bandwidth to minimize the amount of jitter transfer from the video source to the TMDS outputs. Input jitter within the CDR’s PLL bandwidth, < 1 MHz, is transferred to the TMDS outputs. Higher frequency jitter above the CDR loop bandwidth is attenuated, providing a jitter cleaning function to reduce the amount of high frequency jitter from the video source. The retimer is automatically activated at pixel clock above approximately 100 MHz when jitter cleaning is needed for robust operation. The retimer operates at about 100 Mhz – 340 MHz pixel clock (1 – 3.4 Gbps). At pixel clock below about 100 MHz, the TMDS171 automatically bypasses the internal retimer, and operates as a redriver. When the video source changes resolution, the internal retimer starts the acquisition process to determine the input clock frequency and acquire lock to the new data bit streams. During the clock frequency detection period and the retimer acquisition period that last approximately 7 ms, the TMDS drivers can be kept active (default) or programmed to be disabled to avoid sending invalid clock or data to the downstream receiver. The TMDS171 can support retimer mode across the full data rate range of 250 Mbps - 3.4 Gbps by setting DEV_FUNC_MODE bits at reg0Ah[1:0], See Table 9. For compliance testing such as JTOL for 480 Mbps the PLL must be forced to lock.

8.4.2 Redriver Mode

The TMDS171 can function as a redriver which compensates for ISI channel loss. In this mode, power is reduced as the CDR and PLL are turned off. When in automatic mode, the TMDS171 is in redriver mode for data rates < 1.0 Gbps. By using I²C the device can be put in Redriver mode for the complete data range of 250 Mbps to 3.4 Gbps. This is done by writing a 00 to register 0Ah[1:0]. If the link has excessive random jitter then retimer mode is the best operating mode. If the link has excessive random jitter, the retimer mode is the best operating mode. When in redriver mode, the device compensates for ISI loss only. When in redriver mode compliance is not ensured as skew compensation and retiming functions are disabled. If a significant amount of random jitter is present, the system may not pass compliance at the connector.

8.4.3 DDC Functional Description

The TMDS171 solves sink/source level issues by implementing a master/salve control mode for the DDC bus. When the TMDS171 detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC, it transfers the data or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK detects the feedback from the downstream device, the TMDS171 pulls up or pulls down the SDA_SRC bus and delivers the signal to the source.

The DDC link defaults to 100 kbps but can be set to various values including 400 kbps by setting the correct value to address 0Bh through the I²C interface. The DDC lines are 5 V tolerant when the device is powered off. The HPD goes to high impedance when VCC is under low power conditions < 1.5 V.

8.4.4 Mode Selection Functional Description

Mode Selection Definition: reg0Ah[7] is the mode select register, see Table 9. This bit lets the receiver know where the device is located in a system for the purpose of centering the AEQ point. The TMDS171 is targeting sink or dock applications so the default value is 1 which centers the EQ at 12 dB to 13 dB, see Table 12. If the TMDS171 is in a source application the value should be changed to a 0 which centers the EQ at 6.5 dB to 7.5 dB.

8.5.1 Local I²C Overview

The TMDS171 local I²C interface is enabled when I2C_EN/PIN is high. The SCL_CTL and SDA_CTL terminals are used for I²C clock and I²C data respectively. The TMDS171 I²C interface conforms to the two-wire serial interface defined by the I²C Bus Specification, Version 2.1 (January 2000), and supports the fast mode transfer up to 400 kbps.

The device address byte is the first byte received following the START condition from the master device. The 7 bit device address for TMDS171 decides by the combination of EQ_SEL/A0 and A1. Table 4 clarifies the TMDS171 target address.

The typical source application of the TMDS171 is as a retimer in a TV connecting the HDMI input connector and an internal HDMI receiver through flat cables. The register setup can adjust by source side. When TMDS171 used in sink side application, it received data from input connector and transmit to receiver. The local I²C is not 5 V tolerant and only support 3.3 V. Local I2C buses run at 400 kHz supporting fast-mode I²C operation.

The following procedure is followed to write to the TMDS171 I²C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the TMDS171 7-bit address and a zero-value “W/R” bit to indicate a write cycle
2. The TMDS171 acknowledges the address cycle
3. The master presents the sub-address (I²C register within TMDS171) to be written, consisting of one byte of data, MSB-first
4. The TMDS171 acknowledges the sub-address cycle
5. The master presents the first byte of data to be written to the I²C register
6. The TMDS171 acknowledges the sub-address cycle
7. TMDS171 acknowledges the byte transfer
8. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TMDS171
9. The master terminates the write operation by generating a stop condition (P)

The following procedure is followed to read the TMDS171 I²C registers:

1. The master initiates a read operation by generating a start condition (S), followed by the TMDS171 7-bit address and a one-value “W/R” bit to indicate a read cycle
2. The TMDS171 acknowledges the address cycle
3. The TMDS171 transmit the contents of the memory registers MSB-first starting at register 00h.
4. The TMDS171 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I²C master acknowledges reception of each data byte transfer
5. If an ACK is received, the TMDS171 transmits the next byte of data
6. The master terminates the read operation by generating a stop condition (P)

Refer to Table 4 for TMDS171 local I²C register descriptions. Reads from reserved fields not described return zeros, and writes are ignored.

8.5.2 CSR Bit Field Definitions, DEVICE_ID (offset: 00000000 ≈ 00000111) (reset:00h ≈ 07h)

8.5.3 CSR Bit Field Definitions, REV _ID (offset: 00001000) (reset: 01h)

8.5.4 CSR BIT Field Definitions – Misc Control (offset: 00001001) (reset: 02h)

8.5.5 CSR BIT Field Definitions – Misc Control (offset: 00001010) (reset: B1h)

8.5.6 CSR BIT Field Definitions – Misc Control (offset: 00001011) (reset: 00h)

8.5.7 CSR BIT Field Definitions – Misc Control (offset: 00001100) (reset: 00h)

8.5.8 CSR BIT Field Definitions – Equalization Control Register (offset: 00001101) (reset: 01h)

8.5.9 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00001110) (reset: 00h)

8.5.10 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00001111) (reset: 00h)

8.5.11 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010000) (reset: 00h)

8.5.12 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010001) (reset: 00h)

8.5.13 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010010) (reset: 00h)

8.5.14 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010011) (reset: 00h)

8.5.15 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010100) (reset: 00h)

8.5.16 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010101) (reset: 00h)

8.5.17 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010110) (reset: 00h)

8.5.18 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010111) (reset: 00h)

8.5.19 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011000) (reset: 00h)

8.5.20 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011001) (reset: 00h)

8.5.21 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011010) (reset: 00h)

8.5.22 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011011) (reset: 00h)

8.5.23 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011100) (reset: 00h)

8.5.24 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011101) (reset: 00h)

8.5.25 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011110) (reset: 00h)

8.5.26 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011111) (reset: 00h)

8.5.27 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00100000) (reset: 00h)