9.1.1 Application Chain Showing DDC Connections

The DDC circuitry inside the TMDS171 allows multiple stage operation as shown in Figure 56. The retimer devices can be connected to any of the bus segments. The number of devices that can be connected in series is limited by repeater delay/time of flight considerations for the maximum bus speed requirements.

Figure 56. Typical Series Application

9.1.2 DDC Pull Up Resistors

This section is for information only and subject to change depending upon system implementation. The pull-up resistor value is determined by two requirements.

1. The maximum sink current of the I²C buffer: The maximum sink current is 3 mA or slightly higher for an I²C driver supporting standard-mode I²C operation.
Equation 1.
2. The maximum transition time on the bus:

The maximum transition time, T, of an I²C bus is set by an RC time constant, where R is the pull-up resistor value, and C is the total load capacitance. The parameter, k, can be calculated from Equation 2 by solving for t, the times at which certain voltage thresholds are reached. Different input threshold combinations introduce different values of t. Table 32 summarizes the possible values of k under different threshold combinations.

Equation 2.

Equation 3.

From Equation 1, R_up(min) = 5.5 V / 3 mA = 1.83 kΩ to operate the bus under a 5-V pull-up voltage and provide less than 3 mA when the I²C device is driving the bus to a low state. If a higher sink current, for example 4 mA, is allowed, R_up(min) can be as low as 1.375 kΩ.

If DDC working at standard mode of 100 Kbps, the maximum transition time T is fixed, 1 μs, and using the k values from Table 32, the recommended maximum total resistance of the pull-up resistors on an I²C bus can be calculated for different system setups. If DDC working at fast mode of 400 Kbps, the transition time should be set at 300 ns according to I²C specification.

To support the maximum load capacitance specified in the HDMI spec, C_cable(max) = 700 pF/C_(source) = 50 pF/Ci = 50 pF, R(max) can be calculated as shown in Table 33.

To accommodate the 3 mA drive current specification, a narrower threshold voltage range is required to support a maximum 800 pF load capacitance for a standard-mode I²C bus.

9.2.1 Design Requirements

The TMDS171 can be designed into many different applications. In all the applications there are certain requirements for the system to work properly. Two voltage rails are required in order to support lowest power consumption possible. OE pin must have a 200 nF capacitor to ground. This pin can be driven by a processor but the pin needs to change states after voltage rails have stabilized. The best way to configure the device is by using I²C but pin strapping is also provided as I²C is not available in all cases. As sources may have many different naming conventions it is necessary to confirm that the link between the source and the TMDS171 are correctly mapped. A Swap function is provide for the input pins incase signaling if reversed between source and device. Table 34 provides information on expected values in order to perform properly.

9.2.2 Detailed Design Procedure

The TMDS171 is a signal conditioning device that provides several forms of signal conditioning in order to support compliance for HDMI or DVI at a source connector. These forms of signal conditioning are accomplished using receive equalization, retiming, and output driver configurability. The transmitter will drive 2-3” of board trace and connector when compliance is required at the connector.

To design in the TMDS171 the following need to be understood for a source side application:

• Determine the loss profile between the GPU/chipset and the HDMI/DVI connector.
• Based upon this loss profile and signal swing determine optimal location for the TMDS171, in order to pass source electrical compliance. Usually within 2”-3” of the connector
• Use the typical application Figure 57 for information on control pin resistors.
• The TMDS171 has a receiver adaptive equalizer but can also be configured using EQ_SEL control pin.
• Set the VOD, Pre-emphasis, termination, and edge rate levels appropriately to support compliance by using the appropriate VSADJ resistor value and setting PRE_SEL, and TX_TERM_CTL control pins.
• The thermal pad must be connected to ground.
• See Figure 57 for recommended decouple capacitors from V_CC and V_DD pins to Ground

9.2.3 Application Curves

Figure 58. 1080p Compliance Eye

Figure 59. 4k2k30 Compliance Eye

9.2.4 Sink Side Application

For a sink side application HPD needs consideration. The TMDS171 drives the HPD signal to 3.3V which meetings requirements but if 5 V HPD signaling is required the two circuits shown in Figure 60 are required. As sources are not consistent in implementing all aspects of the DDC link it is recommended to configure the TMDS171 as per Figure 60. Another consideration in relationship to how HPD is implemented is the architecture and behavior of the HDMI RX/Scalar.

Figure 60. TMDS171 in Sink Side Application, 5 V HPD Implementation