SLAS671C February   2010  – January 2017 TLV320DAC3100

PRODUCTION DATA.  

1. 1 Device Overview
   1. 1.1 Features
   2. 1.2 Applications
   3. 1.3 Description
   4. 1.4 Functional Block Diagram
2. 2 Revision History
3. 3 Pin Configuration and Functions
   1. 3.1 Pin Attributes
4. 4 Specifications
   1. 4.1  Absolute Maximum Ratings
   2. 4.2  ESD Ratings
   3. 4.3  Recommended Operating Conditions
   4. 4.4  Thermal Information
   5. 4.5  Electrical Characteristics
   6. 4.6  Power Dissipation Ratings
   7. 4.7  I2S, LJF, and RJF Timing in Master Mode
   8. 4.8  I2S, LJF, and RJF Timing in Slave Mode
   9. 4.9  DSP Timing in Master Mode
   10. 4.10 DSP Timing in Slave Mode
   11. 4.11 I2C Interface Timing
   12. 4.12 Typical Characteristics
       1. 4.12.1 DAC Performance
       2. 4.12.2 Class-D Speaker Driver Performance
       3. 4.12.3 Analog Bypass Performance H
       4. 4.12.4 MICBIAS Performance H
5. 5 Parameter Measurement Information
6. 6 Detailed Description
   1. 6.1 Overview
   2. 6.2 Functional Block Diagram
   3. 6.3 Feature Description
      1. 6.3.1  Power-Supply Sequence
      2. 6.3.2  Reset
      3. 6.3.3  Device Start-Up Lockout Times
      4. 6.3.4  PLL Start-Up
      5. 6.3.5  Power-Stage Reset
      6. 6.3.6  Software Power Down
      7. 6.3.7  Audio Analog I/O
      8. 6.3.8  Digital Processing Low-Power Modes
         1. 6.3.8.1 DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
         2. 6.3.8.2 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
         3. 6.3.8.3 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
         4. 6.3.8.4 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
         5. 6.3.8.5 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
         6. 6.3.8.6 DAC Playback on Line Out (10 k-? load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3 V, HPVDD = 3 V
      9. 6.3.9  Analog Signals
         1. 6.3.9.1 MICBIAS
         2. 6.3.9.2 Analog Inputs AIN1 and AIN2
      10. 6.3.10 Audio DAC and Audio Analog Outputs
          1. 6.3.10.1  DAC
             1. 6.3.10.1.1 DAC Processing Blocks
             2. 6.3.10.1.2 DAC Processing Blocks — Details
                1. 6.3.10.1.2.1  Three Biquads, Filter A
                2. 6.3.10.1.2.2  Six Biquads, First-Order IIR, DRC, Filter A or B
                3. 6.3.10.1.2.3  Six Biquads, First-Order IIR, Filter A or B
                4. 6.3.10.1.2.4  IIR, Filter B or C
                5. 6.3.10.1.2.5  Four Biquads, DRC, Filter B
                6. 6.3.10.1.2.6  Four Biquads, Filter B
                7. 6.3.10.1.2.7  Four Biquads, First-Order IIR, DRC, Filter C
                8. 6.3.10.1.2.8  Four Biquads, First-Order IIR, Filter C
                9. 6.3.10.1.2.9  Two Biquads, 3D, Filter A
                10. 6.3.10.1.2.10 Five Biquads, DRC, 3D, Filter A
                11. 6.3.10.1.2.11 Five Biquads, DRC, 3D, Beep Generator, Filter A
             3. 6.3.10.1.3 DAC User-Programmable Filters
                1. 6.3.10.1.3.1 First-Order IIR Section
                2. 6.3.10.1.3.2 Biquad Section
             4. 6.3.10.1.4 DAC Interpolation Filter Characteristics
                1. 6.3.10.1.4.1 Interpolation Filter A
                2. 6.3.10.1.4.2 Interpolation Filter B
                3. 6.3.10.1.4.3 Interpolation Filter C
          2. 6.3.10.2  DAC Digital-Volume Control
          3. 6.3.10.3  Volume Control Pin
          4. 6.3.10.4  Dynamic Range Compression
             1. 6.3.10.4.1 DRC Threshold
             2. 6.3.10.4.2 DRC Hysteresis
             3. 6.3.10.4.3 DRC Hold Time
             4. 6.3.10.4.4 DRC Attack Rate
             5. 6.3.10.4.5 DRC Decay Rate
             6. 6.3.10.4.6 Example Setup for DRC
          5. 6.3.10.5  Headphone Detection
          6. 6.3.10.6  Interrupts
          7. 6.3.10.7  Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25)
          8. 6.3.10.8  Programming DAC Digital Filter Coefficients
          9. 6.3.10.9  Updating DAC Digital Filter Coefficients During PLAY
          10. 6.3.10.10 Digital Mixing and Routing
          11. 6.3.10.11 Analog Audio Routing
              1. 6.3.10.11.1 Analog Output Volume Control
              2. 6.3.10.11.2 Headphone Analog-Output Volume Control
              3. 6.3.10.11.3 Class-D Speaker Analog Output Volume Control
          12. 6.3.10.12 Analog Outputs
              1. 6.3.10.12.1 Headphone Drivers
              2. 6.3.10.12.2 Speaker Drivers
          13. 6.3.10.13 Audio-Output Stage-Power Configurations
          14. 6.3.10.14 DAC Setup
          15. 6.3.10.15 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs
      11. 6.3.11 CLOCK Generation and PLL
          1. 6.3.11.1 PLL
      12. 6.3.12 Timer
      13. 6.3.13 Digital Audio and Control Interface
          1. 6.3.13.1 Digital Audio Interface
             1. 6.3.13.1.1 Right-Justified Mode
             2. 6.3.13.1.2 Left-Justified Mode
             3. 6.3.13.1.3 I2S Mode
             4. 6.3.13.1.4 DSP Mode
          2. 6.3.13.2 Primary and Secondary Digital Audio Interface Selection
          3. 6.3.13.3 Control Interface
             1. 6.3.13.3.1 I2C Control Mode
   4. 6.4 Register Map
      1. 6.4.1 TLV320DAC3100 Register Map
      2. 6.4.2 Registers
         1. 6.4.2.1 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs
         2. 6.4.2.2 Control Registers, Page 1: DAC, Power-Controls, and MISC Logic-Related Programmability
         3. 6.4.2.3 Control Registers, Page 3: MCLK Divider for Programmable Delay Timer
         4. 6.4.2.4 Control Registers, Page 8: DAC Programmable Coefficients RAM Buffer A (1:63)
         5. 6.4.2.5 Control Registers, Page 9: DAC Programmable Coefficients RAM Buffer A (65:127)
         6. 6.4.2.6 Control Registers, Page 12: DAC Programmable Coefficients RAM Buffer B (1:63)
         7. 6.4.2.7 Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127)
7. 7 Application and Implementation
   1. 7.1 Application Information
   2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
8. 8 Power Supply Recommendations
9. 9 Layout
   1. 9.1 Layout Guidelines
   2. 9.2 Layout Example
10. 10Device and Documentation Support
    1. 10.1 Device Support
       1. 10.1.1 Device Nomenclature
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information