SLAS671C February 2010 – January 2017 TLV320DAC3100
PRODUCTION DATA.
- 1 Device Overview
- 2 Revision History
- 3 Pin Configuration and Functions
-
4 Specifications
- 4.1 Absolute Maximum Ratings
- 4.2 ESD Ratings
- 4.3 Recommended Operating Conditions
- 4.4 Thermal Information
- 4.5 Electrical Characteristics
- 4.6 Power Dissipation Ratings
- 4.7 I2S, LJF, and RJF Timing in Master Mode
- 4.8 I2S, LJF, and RJF Timing in Slave Mode
- 4.9 DSP Timing in Master Mode
- 4.10 DSP Timing in Slave Mode
- 4.11 I2C Interface Timing
- 4.12 Typical Characteristics
- 5 Parameter Measurement Information
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Power-Supply Sequence
- 6.3.2 Reset
- 6.3.3 Device Start-Up Lockout Times
- 6.3.4 PLL Start-Up
- 6.3.5 Power-Stage Reset
- 6.3.6 Software Power Down
- 6.3.7 Audio Analog I/O
- 6.3.8
Digital Processing Low-Power Modes
- 6.3.8.1 DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
- 6.3.8.2 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
- 6.3.8.3 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
- 6.3.8.4 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
- 6.3.8.5 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
- 6.3.8.6 DAC Playback on Line Out (10 k-? load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3 V, HPVDD = 3 V
- 6.3.9 Analog Signals
- 6.3.10
Audio DAC and Audio Analog Outputs
- 6.3.10.1
DAC
- 6.3.10.1.1 DAC Processing Blocks
- 6.3.10.1.2
DAC Processing Blocks — Details
- 6.3.10.1.2.1 Three Biquads, Filter A
- 6.3.10.1.2.2 Six Biquads, First-Order IIR, DRC, Filter A or B
- 6.3.10.1.2.3 Six Biquads, First-Order IIR, Filter A or B
- 6.3.10.1.2.4 IIR, Filter B or C
- 6.3.10.1.2.5 Four Biquads, DRC, Filter B
- 6.3.10.1.2.6 Four Biquads, Filter B
- 6.3.10.1.2.7 Four Biquads, First-Order IIR, DRC, Filter C
- 6.3.10.1.2.8 Four Biquads, First-Order IIR, Filter C
- 6.3.10.1.2.9 Two Biquads, 3D, Filter A
- 6.3.10.1.2.10 Five Biquads, DRC, 3D, Filter A
- 6.3.10.1.2.11 Five Biquads, DRC, 3D, Beep Generator, Filter A
- 6.3.10.1.3 DAC User-Programmable Filters
- 6.3.10.1.4 DAC Interpolation Filter Characteristics
- 6.3.10.2 DAC Digital-Volume Control
- 6.3.10.3 Volume Control Pin
- 6.3.10.4 Dynamic Range Compression
- 6.3.10.5 Headphone Detection
- 6.3.10.6 Interrupts
- 6.3.10.7 Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25)
- 6.3.10.8 Programming DAC Digital Filter Coefficients
- 6.3.10.9 Updating DAC Digital Filter Coefficients During PLAY
- 6.3.10.10 Digital Mixing and Routing
- 6.3.10.11 Analog Audio Routing
- 6.3.10.12 Analog Outputs
- 6.3.10.13 Audio-Output Stage-Power Configurations
- 6.3.10.14 DAC Setup
- 6.3.10.15 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs
- 6.3.10.1
DAC
- 6.3.11 CLOCK Generation and PLL
- 6.3.12 Timer
- 6.3.13 Digital Audio and Control Interface
- 6.4
Register Map
- 6.4.1 TLV320DAC3100 Register Map
- 6.4.2
Registers
- 6.4.2.1 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs
- 6.4.2.2 Control Registers, Page 1: DAC, Power-Controls, and MISC Logic-Related Programmability
- 6.4.2.3 Control Registers, Page 3: MCLK Divider for Programmable Delay Timer
- 6.4.2.4 Control Registers, Page 8: DAC Programmable Coefficients RAM Buffer A (1:63)
- 6.4.2.5 Control Registers, Page 9: DAC Programmable Coefficients RAM Buffer A (65:127)
- 6.4.2.6 Control Registers, Page 12: DAC Programmable Coefficients RAM Buffer B (1:63)
- 6.4.2.7 Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127)
- 7 Application and Implementation
- 8 Power Supply Recommendations
- 9 Layout
- 10Device and Documentation Support
- 11Mechanical Packaging and Orderable Information
1 Device Overview
1.1 Features
- Stereo Audio DAC with 95-dB SNR
- Supports 8-kHz to 192-kHz Sample Rates
- Mono Class-D BTL Speaker Driver (2.5 W Into 4-Ω or 1.6 W Into 8-Ω)
- Two Single-Ended Inputs With Mixing and Output Level Control
- Stereo Headphone/Lineout and Mono Class-D Speaker Outputs Available
- Microphone Bias
- Headphone Detection
- 25 Built-in Digital Audio Processing Blocks (PRB_P1 – PRB_P25) Providing Biquad and FIR Filters, DRC, and 3-D Structures
- Digital Mixing Capability
- Pin Control or Register Control for Digital-Playback Volume-Control Settings
- Digital Sine-Wave Generator for Beeps and Key Clicks (PRB_P25)
- Programmable PLL for Flexible Clock Generation
- I2S, Left-Justified, Right-Justified, DSP, and TDM Audio Interfaces
- I2C Control With Register Auto-Increment
- Full Power-Down Control
- Power Supplies:
- Analog: 2.7 V–3.6 V
- Digital Core: 1.65 V–1.95 V
- Digital I/O: 1.1 V–3.6 V
- Class-D: 2.7 V–5.5 V (SPKVDD ≥ AVDD)
- 5-mm × 5-mm 32-VQFN Package
1.2 Applications
- Portable Audio Devices
- Mobile Internet Devices
- eBooks
1.3 Description
The TLV320DAC3100 device is a low-power, highly integrated, high-performance stereo audio DAC with 24-bit stereo playback and digital audio processing blocks.
The device integrates headphone drivers and speaker drivers. The mono speaker driver can drive loads down to 4 Ω. The TLV320DAC3100 device has a suite of built-in processing blocks for digital audio processing. The digital audio data format is programmable to work with popular audio standard protocols (I2S, left/right-justified) in master, slave, DSP, and TDM modes. Bass boost, treble, or EQ can be supported by the programmable digital signal-processing block. An on-chip PLL provides the high-speed clock needed by the digital signal-processing block. The volume level can be controlled either by pin control or by register control. The audio functions are controlled using the I2C serial bus.
The TLV320DAC3100 device has a programmable digital sine-wave generator and is available in a 32-pin VQFN package.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| TLV320DAC3100 | VQFN (32) | 5.00 mm × 5.00 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
1.4 Functional Block Diagram
