ZHCSGM5A August 2017 – November 2017 TLV320AIC3109-Q1
PRODUCTION DATA.
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Power-supply voltage | AVDD to AVSS, DRVDD to DRVSS | –0.3 | 3.9 | V |
| AVDD to DRVSS | –0.3 | 3.9 | ||
| IOVDD to DVSS | –0.3 | 3.9 | ||
| DVDD to DVSS | –0.3 | 2.5 | ||
| AVDD to DRVDD | –0.1 | 0.1 | ||
| Analog input voltage | Analog input voltage to AVSS | –0.3 | AVDD + 0.3 | V |
| Digital input voltage | Digital input voltage to DVSS | –0.3 | IOVDD + 0.3 | V |
| Temperature | Operating ambient, TA | –40 | 105 | °C |
| Junction, TJ | –40 | 125 | ||
| Storage, Tstg | –40 | 150 | ||
Figure 1. I2S, Left-Justified and Right-Justified Format Timing in Master Mode
Figure 2. DSP Timing in Master Mode
Figure 3. I2S, Left-Justified and Right-Justified Format Timing in Slave Mode
Figure 4. DSP Timing in Slave Mode