ZHCSOF3G April 2006 – July 2021 TLV320AIC3106
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
| PARAMETER | IOVDD = 1.1 V | IOVDD = 3.3 V | UNIT | |||
|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | |||
| I2S/LJF/RJF Timing in Master Mode | ||||||
| td(WS) | ADWS/WCLK delay time | 50 | 15 | ns | ||
| td(DO-WS) | ADWS/WCLK to DOUT delay time | 50 | 20 | ns | ||
| td(DO-BCLK) | BCLK to DOUT delay time | 50 | 15 | ns | ||
| ts(DI) | DIN setup time | 10 | 6 | ns | ||
| th(DI) | DIN hold time | 10 | 6 | ns | ||
| tr | Rise time | 30 | 10 | ns | ||
| tf | Fall time | 30 | 10 | ns | ||
| DSP Timing in Master Mode | ||||||
| td(WS) | ADWS/WCLK delay time | 50 | 15 | ns | ||
| td(DO-BCLK) | BCLK to DOUT delay time | 50 | 15 | ns | ||
| ts(DI) | DIN setup time | 10 | 6 | ns | ||
| th(DI) | DIN hold time | 10 | 6 | ns | ||
| tr | Rise time | 30 | 10 | ns | ||
| tf | Fall time | 30 | 10 | ns | ||
| I2S/LJF/RJF Timing in Slave Mode | ||||||
| tH(BCLK) | BCLK high period | 70 | 35 | ns | ||
| tL(BCLK) | BCLK low period | 70 | 35 | ns | ||
| ts(WS) | ADWS/WCLK setup time | 10 | 6 | ns | ||
| th(WS) | ADWS/WCLK hold time | 10 | 6 | ns | ||
| td(DO-WS) | ADWS/WCLK to DOUT delay time (for LJF Mode only) | 50 | 35 | ns | ||
| td(DO-BCLK) | BCLK to DOUT delay time | 50 | 20 | ns | ||
| ts(DI) | DIN setup time | 10 | 6 | ns | ||
| th(DI) | DIN hold time | 10 | 6 | ns | ||
| tr | Rise time | 8 | 4 | ns | ||
| tf | Fall time | 8 | 4 | ns | ||
| DSP Timing in Slave Mode | ||||||
| tH(BCLK) | BCLK high period | 70 | 35 | ns | ||
| tL(BCLK) | BCLK low period | 70 | 35 | ns | ||
| ts(WS) | ADWS/WCLK setup time | 10 | 8 | ns | ||
| th(WS) | ADWS/WCLK hold time | 10 | 8 | ns | ||
| td(DO-BCLK) | BCLK to DOUT delay time | 50 | 20 | ns | ||
| ts(DI) | DIN setup time | 10 | 6 | ns | ||
| th(DI) | DIN hold time | 10 | 6 | ns | ||
| tr | Rise time | 8 | 4 | ns | ||
| tf | Fall time | 8 | 4 | ns | ||