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ZHCSMC0A December 2020 – April 2022 TLIN1029A-Q1

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

D|8
- MSOI002K
DRB|8
- MPDS118K

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

DRB|8
- QFND619

訂購信息

7.7 Duty Cycle Characteristics

parameters valid across -40℃ ≤ T_A ≤ 125℃ (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
D1_12V	Duty Cycle 1 (ISO/DIS 17987 Param 27) ⁽³⁾	TH_REC(MAX) = 0.744 x V_SUP TH_DOM(MAX) = 0.581 x V_SUP, V_SUP = 7 V to 18 V, t_BIT = 50 μs (20 kbps), D1 = t_{BUS_rec(min)}/(2 x t_BIT) (See Figure 8-10, Figure 8-11)	0.396
D1_12V	Duty Cycle 1 (ISO/DIS 17987 Param 27) ⁽³⁾	TH_REC(MAX) = 0.625 x V_SUP, TH_DOM(MAX) = 0.581 x V_SUP, V_SUP = 4 V to 7 V, t_BIT = 50 μs (20 kbps), D1 = t_{BUS_rec(min)}/(2 x t_BIT) (See Figure 8-10, Figure 8-11)	0.396
D1	Duty cycle 1 ⁽¹⁾ ⁽²⁾	TH_REC(MAX) = 0.744 x V_SUP, TH_DOM(MAX) = 0.581 x V_SUP, V_SUP = 7 V to 18 V, t_BIT = 52 μs D1 = t_{BUS_rec(min)}/(2 x t_BIT) (See Figure 8-10, Figure 8-11)	0.396
D2_12V	Duty Cycle 2 (ISO/DIS 17987 Param 28) ⁽³⁾	TH_REC(MIN) = 0.422 x V_SUP, TH_DOM(MIN) = 0.284 x V_SUP, V_SUP = 7 V to 18 V, t_BIT = 50 μs (20 kbps), D2 = t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure 8-10, Figure 8-11)		0.581
D2_12V	Duty Cycle 2 ⁽³⁾	TH_REC(MIN) = 0.546 x V_SUP, TH_DOM(MIN) = 0.4 x V_SUP, V_SUP = 4 V to 7 V, t_BIT = 50 μs (20 kbps), D2 = t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure 8-10, Figure 8-11)		0.581
D2	Duty Cycle 2 ⁽¹⁾ ⁽²⁾	TH_REC(MIN) = 0.422 x V_SUP, TH_DOM(MIN) = 0.284 x V_SUP, V_SUP = 7 V to 18 V, t_BIT = 52 μs D2 = t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure 8-10, Figure 8-11)		0.581
D3_12V	Duty Cycle 3 (ISO/DIS 17987 Param 29) ⁽³⁾	TH_REC(MAX) = 0.778 x V_SUP, TH_DOM(MAX) = 0.616 x V_SUP, V_SUP = 7 V to 18 V, t_BIT = 96 μs (10.4 kbps), D3 = t_{BUS_rec(min)}/(2 x t_BIT) (See Figure 8-10, Figure 8-11)	0.417
D3_12V	Duty Cycle 3 ⁽³⁾	TH_REC(MAX) = 0.645 x V_SUP, TH_DOM(MAX) = 0.616 x V_SUP, V_SUP = 4 V to 7 V, t_BIT = 96 μs (10.4 kbps), D3 = t_{BUS_rec(min)}/(2 x t_BIT) (See Figure 8-10, Figure 8-11)	0.417
D3	Duty Cycle 3 ⁽¹⁾ ⁽²⁾	TH_REC(MAX) = 0.778 x V_SUP TH_DOM(MAX) = 0.616 x V_SUP V_SUP = 7 V to 18 V, t_BIT = 96 μs D3 = t_{BUS_rec(min)}/(2 x t_BIT) (See Figure 8-10, Figure 8-11)	0.417
D4_12V	Duty Cycle 4 (ISO/DIS 17987 Param 30) ⁽³⁾	TH_REC(MIN) = 0.389 x V_SUP, TH_DOM(MIN) = 0.251 x V_SUP, V_SUP = 7 V to 18 V, t_BIT = 96 μs (10.4 kbps), D4 = t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure 8-10, Figure 8-11)		0.59
D4_12V	Duty Cycle 4 ⁽³⁾	TH_REC(MIN) = 0.422 x V_SUP, TH_DOM(MIN) = 0.284 x V_SUP, V_SUP = 4 V to 7 V, t_BIT = 96 μs (10.4 kbps), D4 = t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure 8-10, Figure 8-11)		0.59
D4	Duty Cycle 4 ⁽¹⁾ ⁽²⁾	TH_REC(MIN) = 0.389 x V_SUP TH_DOM(MIN) = 0.251 x V_SUP V_SUP = 7 V to 18 V, t_BIT = 96 μs D4 = t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure 8-10, Figure 8-11)		0.59
D1_LB	Duty cycle 1 at low battery ⁽¹⁾ ⁽²⁾	TH_REC(MAX) = 0.665 x V_SUP, TH_DOM(MAX) = 0.499 x V_SUP, V_SUP = 5.5 V to 7 V, t_BIT = 52 μs	0.396
D2_LB	Duty cycle 2 at low battery ⁽¹⁾ ⁽²⁾	TH_REC(MAX) = 0.496 x V_SUP TH_DOM(MAX) = 0.361 x V_SUP V_SUP = 6.1 V to 7 V, t_BIT = 52 μs		0.581
D3_LB	Duty cycle 3 at low battery ⁽¹⁾ ⁽²⁾	TH_REC(MAX) = 0.665 x V_SUP, TH_DOM(MAX) = 0.499 x V_SUP, V_SUP = 5.5 V to 7 V, t_BIT = 96 μs	0.396
D4_LB	Duty cycle 4 at low battery ⁽¹⁾ ⁽²⁾	TH_REC(MAX) = 0.496 x V_SUP TH_DOM(MAX) = 0.361 x V_SUP V_SUP = 6.1 V to 7 V, t_BIT = 96 μs		0.581
Tr-d max	Transmitter propagation delay timings for the duty cycle⁽¹⁾ ⁽²⁾ Recessive to dominant	TH_REC(MAX) = 0.744 x V_SUP, TH_DOM(MAX) = 0.581 x V_SUP 7 V ≤ V_SUP ≤ 18 V, t_BIT = 52 μs t_{REC(MAX)_D1} - t_{DOM(MIN)_D1}		10.8	μs
Td-r max	Transmitter propagation delay timings for the duty cycle⁽¹⁾ ⁽²⁾ Dominant to recessive	TH_REC(MAX) = 0.422 x V_SUP, TH_DOM(MAX) = 0.284 x V_SUP 7 V ≤ V_SUP ≤ 18 V, t_BIT = 52 μs t_{DOM(MAX)_D2} - t_{REC(MIN)_D2}		8.4	μs
Tr-d max	Transmitter propagation delay timings for the duty cycle⁽¹⁾ ⁽²⁾ Recessive to dominant	TH_REC(MAX) = 0.778 x V_SUP TH_DOM(MAX) = 0.616 x V_SUP 7 V ≤ V_SUP ≤ 18 V, t_BIT = 96 μs t_{REC(MAX)_D3} - t_{DOM(MIN)_D3}		15.9	μs
Td-r max	Transmitter propagation delay timings for the duty cycle⁽¹⁾ ⁽²⁾ Dominant to recessive	TH_REC(MIN) = 0.389 x V_SUP TH_DOM(MIN) = 0.251 x V_SUP 7 V ≤ V_SUP ≤ 18 V, t_BIT = 96 μs t_{DOM(MAX)_D4} - t_{REC(MIN)_D4}		17.28	μs
Tr-d max_low	Low battery transmitter propagation delay timings for the duty cycle⁽¹⁾ ⁽²⁾ Recessive to dominant	TH_REC(MAX) = 0.665 x V_SUP, TH_DOM(MAX) = 0.499 x V_SUP 5.5 V ≤ V_SUP ≤ 7 V, t_BIT = 52 μs t_{REC(MAX)_low} - t_{DOM(MIN)_low}		10.8	μs
Td-r max_low	Low battery transmitter propagation delay timings for the duty cycle⁽¹⁾ ⁽²⁾ Dominant to recessive	TH_REC(MAX) = 0.496 x V_SUP TH_DOM(MAX) = 0.361 x V_SUP 6.1 V ≤ V_SUP ≤ 7 V, t_BIT = 52 μs t_{DOM(MAX)_low} - t_{REC(MIN)_low}		8.4	μs

(1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩ and 899 pF/20 kΩ

(2) SAE 2602 responder node load conditions: 5.5 nF/875 Ω and 899 pF/900 Ω

(3) ISO 17987 bus load conditions (C_LINBUS, R_LINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.