ZHCSMC0A December 2020 – April 2022 TLIN1029A-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 說明（續）
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 LIN (Local Interconnect Network) Bus
- 9.3.2 TXD (Transmit Input and Output)
- 9.3.3 RXD (Receive Output)
- 9.3.4 VSUP (Supply Voltage)
- 9.3.5 GND (Ground)
- 9.3.6 EN (Enable Input)
- 9.3.7 Protection Features
- 9.3.8 TXD Dominant Time Out (DTO)
- 9.3.9 Bus Stuck Dominant System Fault: False Wake Up Lockout
- 9.3.10 Thermal Shutdown
- 9.3.11 Under Voltage on VSUP
- 9.3.12 Unpowered Device and LIN Bus
- 9.4 Device Functional Modes
- 10Application Information Disclaimer
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
- DRB|8
訂購信息
10.2.3 Application Curves
The below figures show the propagation delay from the TXD pin to the LIN pin for both dominant to recessive and recessive to dominant edges. Device was configured in commander mode with external pull-up resistor (1 kΩ) and 680 pF bus capacitance.
Figure 10-2 Recessive to Dominant Propagation
Figure 10-3 Dominant to Recessive Propagation