ZHCSK68B August 2019 – June 2022 TLIN1028-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| RXD OUTPUT TERMINAL (OPEN-DRAIN) | ||||||
| VOL | Output low voltage | Based upon a 2 kΩ to 10 kΩ external pull-up to VCC | 0.2 | VCC | ||
| IOL | Low-level output current, open-drain | LIN = 0 V, RXD = 0.4 V | 1.5 | mA | ||
| ILKG | Leakage current, high-level | LIN = VSUP, RXD = VCC | –5 | 0 | 5 | μA |
| TXD INPUT TERMINAL | ||||||
| VIL | Low-level input voltage | –0.3 | 0.8 | V | ||
| VIH | High-level input voltage | 2 | 5.5 | V | ||
| IIH | High-level input leakage current | TXD = high | –5 | 0 | 5 | μA |
| RTXD | Internal pull-up resistor value | 125 | 350 | 800 | k? | |
| LIN TERMINAL (REFERENCED TO VSUP) | ||||||
| VOH | High-level output voltage(1) | LIN recessive, TXD = high, IO = 0 mA, VSUP = 5.5 V to 36 V | 0.85 | VSUP | ||
| VOL | Low-level output voltage(1) | LIN dominant, TXD = low, VSUP = 5.5 V to 36 V | 0.2 | VSUP | ||
| VIH | High-level input voltage(1) | LIN recessive, TXD = high, IO = 0 mA, VSUP = 5.5 V to 36 V | 0.47 | 0.6 | VSUP | |
| VIL | Low-level input voltage(1) | LIN dominant, TXD = low, VSUP = 5.5 V to 36 V | 0.4 | 0.53 | VSUP | |
| VSUP_NON_OP | VSUP where impact of recessive LIN bus < 5% (ISO/DIS 17987 Param 11) | TXD & RXD open, VLIN = 5.5 V to 42 V, Bus Load = 60 kΩ + diode and 1.1 kΩ + diode | –0.3 | 42 | V | |
| I BUS_LIM | Limiting current (ISO/DIS 17987 Param 12) | TXD = 0 V, VLIN = 36 V, RMEAS = 440 ?, VSUP = 36 V, VBUSdom < 4.518 V; Figure 8-6 |
40 | 90 | 200 | mA |
| I BUS_PAS_dom | Receiver leakage current, dominant (ISO/DIS 17987 Param 13) | VLIN = 0 V, VSUP = 12 V Driver off/recessive, RMEAS = 499 ?; Figure 8-7 | –1 | mA | ||
| I BUS_PAS_rec1 | Receiver leakage current, recessive (ISO/DIS 17987 Param 14) | VLIN ≥ VSUP, 5.5 V ≤ VSUP ≤ 36 V Driver off, RMEAS = 1 k?; Figure 8-8 | 20 | μA | ||
| I BUS_PAS_rec2 | Receiver leakage current, recessive (ISO/DIS 17987 Param 14) | VLIN = VSUP, Driver off, RMEAS = 1 k?; Figure 8-8 | –8 | 8 | μA | |
| I BUS_NO_GND | Leakage current, loss of ground (ISO/DIS 17987 Param 15) | GND = VSUP, VSUP = 12 V, 0 V ≤ VLIN ≤ 28 V, RMEAS = 1 k?; Figure 8-9 | –1 | 1 | mA | |
| IBUS_NO_BAT | Leakage current, loss of supply (ISO/DIS 17987 Param 16) | 0 V ≤ VLIN ≤ 28 V, VSUP = GND, RMEAS = 10 k?; Figure 8-10 | 8 | μA | ||
| VBUSdom | Low-level input voltage (ISO/DIS 17987 Param 17) | LIN dominant (including LIN dominant for wake up); Figure 8-3, Figure 8-4 | 0.4 | VSUP | ||
| VBUSrec | High-level input voltage (ISO/DIS 17987 Param 18) | LIN recessive; Figure 8-3, Figure 8-4 | 0.6 | VSUP | ||
| VBUS_CNT | Receiver center threshold (ISO/DIS 17987 Param 19) | VBUS_CNT = (VIL + VIH)/2; Figure 8-3, Figure 8-4 | 0.475 | 0.5 | 0.525 | VSUP |
| VHYS | Hysteresis voltage (ISO/DIS 17987 Param 20)(2) | VHYS = (VIL - VIH); Figure 8-3, Figure 8-4 | 0.07 | 0.175 | VSUP | |
| VSERIAL_DIODE | Serial diode LIN term pull-up path (ISO/DIS 17987 Param 21) | By design and characterization | 0.4 | 0.7 | 1.0 | V |
| RPU | Internal Pull-up resistor to VSUP (ISO/DIS 17987 Param 26) | Normal and Standby modes | 20 | 45 | 60 | k? |
| IRSLEEP | Pull-up current source to VSUP | Sleep mode, VSUP = 12 V, LIN = GND | –20 | –2 | μA | |
| CLINPIN | Capacitance of the LIN pin (6) | 25 | pF | |||
| EN INPUT TERMINAL | ||||||
| VIH | High-level input voltage | 2 | 5.5 | V | ||
| VIL | Low-level input voltage | –0.3 | 0.8 | V | ||
| VHYS | Hysteresis voltage | By design and characterization | 30 | 500 | mV | |
| IIL | Low-level input current | EN = Low | –6 | 0 | 6 | μA |
| REN | Internal pull-down resistor | 125 | 350 | 800 | k? | |
| nRST TERMINAL (OPEN DRAIN OUTPUT) | ||||||
| ILKG | Leakage current, high-level | LIN = VSUP, nRST = VCC | –6 | 6 | μA | |
| VOL | Low-level output voltage | Based upon external pull up to VCC | 0.2 | VCC | ||
| IOL | Low-level output current, open-drain | LIN = 0 V, nRST = 0.4 V | 1.5 | mA | ||
| DUTY CYCLE CHARACTERISTICS | ||||||
| D1 | Duty Cycle 1 (ISO/DIS 17987 Param 27 and J2602 Normal battery)(3)(4) | THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 7 V to 18 V, tBIT = 50/52 μs, D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-11, Figure 8-12) |
0.396 | |||
| D2 | Duty Cycle 2 (ISO/DIS 17987 Param 28 and J2602 Normal battery)(3)(4) | THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 7.6 V to 18 V, tBIT = 50/52 μs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-11, Figure 8-12) |
0.581 | |||
| D3 | Duty Cycle 3 (ISO/DIS 17987 Param 29 and J2602 Normal battery)(3)(4) | THREC(MAX) = 0.778 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 7 V to 18 V, tBIT = 96 μs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-11, Figure 8-12) |
0.417 | |||
| D4 | Duty Cycle 4 (ISO/DIS 17987 Param 30 and J2602 Normal battery)(3)(4) | THREC(MIN) = 0.389 x VSUP, THDOM(MIN) = 0.251 x VSUP, VSUP = 7.6 V to 18 V, tBIT = 96 μs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-11, Figure 8-12) |
0.59 | |||
| D1LB | Duty Cycle 1 J2602 Low battery (4)(5) |
THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP, VSUP = 5.5 V to 7 V, tBIT = 50/52 μs, D1LB = tBUS_rec(min)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.396 | |||
| D2LB | Duty Cycle 2 J2602 Low battery (4)(5) |
T THREC(MIN) = 0.496 x VSUP, THDOM(MIN) = 0.361 x VSUP, VSUP = 6.1 V to 7.6 V, tBIT = 50/52 μs, D2LB = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.581 | |||
| D3LB | Duty Cycle 3 J2602 Low battery (4)(5) |
THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP, VSUP = 5.5 V to 7 V, tBIT = 96 μs, D3LB = tBUS_rec(min)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.417 | |||
| D4LB | Duty Cycle 4 J2602 Low battery (4)(5) |
T THREC(MIN) = 0.496 x VSUP, THDOM(MIN) = 0.361 x VSUP, VSUP = 6.1 V to 7.6 V, tBIT = 96 μs, D4LB = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.59 | |||