ZHCSK68B August 2019 – June 2022 TLIN1028-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY VOLTAGE AND CURRENT | ||||||
| VSUP | Operational supply voltage (ISO/DIS 17987 Param 10)(2) | Device is operational beyond the LIN defined nominal supply voltage range. See Figure 8-1 and Figure 8-2 | 5.5 | 36 | V | |
| VSUP | Nominal supply voltage (ISO/DIS 17987 Param 10)(2) | Normal and Standby Modes: Ramp VSUP while LIN signal is a 10 kHz square wave with 50 % duty cycle and swing between 5.5 V ≤ VLIN ≤ 28 V. See Figure 8-1 and Figure 8-2 | 5.5 | 28 | V | |
| Sleep Mode | 5.5 | 28 | V | |||
| UVSUPR | Under voltage VSUP threshold | Ramp Up | 3.5 | 4.2 | V | |
| UVSUPF | Under voltage VSUP threshold | Ramp Down | 1.8 | 2.1 | 2.7 | V |
| UVHYS | Delta hysteresis voltage for VSUP under voltage threshold | 1.5 | V | |||
| ISUP | Transceiver and LDO supply current (D Package) | Transceiver normal mode dominant plus LDO output | 80 | mA | ||
| ISUP | Transceiver and LDO supply current (DRB and DDA Packages) | Transceiver normal mode dominant plus LDO output | 135 | mA | ||
| ISUPTRXDOM | Supply current transceiver only | Normal Mode: EN = VCC, bus dominant: total bus load where RLIN ≥ 500 ? and CLIN ≤ 10 nF | 1.2 | 5 | mA | |
| Standby Mode: EN = 0 V, bus dominant: total bus load where RLIN ≥ 500 ? and CLIN ≤ 10 nF | 1 | 2.1 | mA | |||
| ISUPTRXREC | Supply current transceiver only(3) | Normal Mode: EN = VCC, Bus recessive: LIN = VSUP, |
450 | 775 | μA | |
| Standby Mode: EN = 0 V, LIN = recessive = VSUP, IOH from processor ≤ 1 μA | 38 | 55 | μA | |||
| Added Standby Mode current through the RXD pull-up resistor with a value of 100 k?: EN = 0 V, LIN = recessive = VSUP, RXD = GND(1) | 55 | |||||
| ISUPTRXSLP | Sleep mode supply current transceiver only | 5.5 V < VSUP ≤ 28 V, LIN = VSUP, EN = 0 V, TXD and RXD floating | 17 | 33 | μA | |
| REGULATED OUTPUT VCC | ||||||
| VCC | Regulated output (D package) | VSUP = 5.5 to 28 V, ICC = 1 to 70 mA | –2 | 2 | % | |
| VCC | Regulated output (DRB and DDA package) | VSUP = 5.5 to 28 V, ICC = 1 to 125 mA | –2 | 2 | % | |
| ?VCC(?VSUP) | Line regulation | VSUP = 5.5 to 28 V, ΔVCC, ICC = 10 mA | 50 | mV | ||
| ?VCC(?VSUPL) | Load regulation (DRB and DDA package) | ICC = 1 to 125 mA, VSUP = 14 V, ΔVCC | 50 | mV | ||
| ?VCC(?VSUPL) | Load regulation (D package) | ICC = 1 to 70 mA, VSUP = 14 V, ΔVCC | 50 | mV | ||
| VDROP | Dropout voltage (5 V LDO) (DRB and DDA package) | VSUP – VCC, ICC = 125 mA; | 300 | 600 | mV | |
| VDROP | Dropout voltage (5 V LDO) (D package) | VSUP – VCC, ICC = 70 mA; | 300 | 600 | mV | |
| VDROP | Dropout voltage (3.3 V LDO) (DRB and DDA package) | VSUP – VCC, ICC = 125 mA; | 350 | 700 | mV | |
| VDROP | Dropout voltage (3.3 V LDO) (D package) | VSUP – VCC, ICC = 70 mA; | 350 | 700 | mV | |
| UVCC5R | Under voltage 5 V VCC threshold | Ramp Up | 4.7 | 4.86 | V | |
| UVCC5F | Under voltage 5 V VCC threshold | Ramp Down | 4.2 | 4.45 | V | |
| UVCC33R | Under voltage 3.3 V VCC threshold (3) | Ramp Up | 2.9 | 3.1 | V | |
| UVCC33F | Under voltage 3.3 V VCC threshold(3) | Ramp Down | 2.5 | 2.75 | V | |
| tDET(UVCC) | VCC undervoltage deglitch time. An UVCC event will not be recognized unless the duration is longer than this.(3) | CnRST = 20pF | 1 | 15 | μs | |
| ICCOUT | Output current (D Package) | VCC in regulation with 12 V VSUP | 0 | 70 | mA | |
| ICCOUT | Output current (DRB and DDA package) | VCC in regulation with 12 V VSUP | 0 | 125 | mA | |
| ICCOUTL | Output current limit | VCC short to ground | 275 | mA | ||
| PSRR | Power supply rejection ratio(3) | VRIP = 0.5 VPP, Load = 10 mA, ? = 100 Hz, CO = 10 μF | 60 | dB | ||
| TSDR | Thermal shutdown temperature | Internal junction temperature - rising | 165 | °C | ||
| TSDF | Thermal shutdown temperature | Internal junction temperature - falling | 150 | °C | ||
| TSDHYS | Thermal shutdown hysteresis | 10 | °C | |||