ZHCSUT0D October 2001 – February 2024 TFP410
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| DC SPECIFICATIONS | ||||||
| VIH | High-level input voltage (Data, DE, VSYNC, HSYNC, and IDCK+/- CMOS inputs) | VREF = DVDD | 0.7VDD | V | ||
| 0.5V ≤ V ≤ 0.95V | VREF + 0.2 | |||||
| High-level input voltage (all other CMOS inputs) | 0.7VDD | |||||
| VIL | Low-level input voltage (Data, DE, VSYNC, HSYNC, and IDCK+/- CMOS inputs) | VREF = DVDD | 0.3VDD | V | ||
| 0.5V ≤V ≤ 0.95V | VREF – 0.2 | |||||
| Low-level input voltage (all other CMOS inputs) | 0.3VDD | |||||
| VOH | High-level digital output voltage (open-drain output) | VDD = 3V, IOH = 20μA | 2.4 | V | ||
| VOL | Low-level digital output voltage (open-drain output) | VDD = 3.6V, IOL = 4mA | 0.4 | V | ||
| IIH | High-level input current | VI = 3.6V | ±25 | μA | ||
| IIL | Low-level input current | VI = 0 | ±25 | μA | ||
| VH | DVI single-ended high-level output voltage | AVDD = 3.3V ± 5%, RT(1) = 50Ω ± 10%, RTFADJ = 510Ω ± 1% |
AVDD – 0.01 | AVDD + 0.01 | V | |
| VL | DVI single-ended low-level output voltage | AVDD – 0.6 | AVDD – 0.4 | V | ||
| VSWING | DVI single-ended output swing voltage | 400 | 600 | mVP-P | ||
| VOFF | DVI single-ended standby/off output voltage | AVDD – 0.01 | AVDD + 0.01 | V | ||
| IPD | Power-down current(3) | 200 | 500 | μA | ||
| IIDD | Normal power supply current | Worst-case pattern(2) | 200 | 250 | mA | |
| AC SPECIFICATIONS | ||||||
| f(IDCK) | IDCK frequency | 25 | 165 | MHz | ||
| tr | DVI output rise time (20-80%)(4) | f(IDCK) = 165MHz | 75 | 240 | ps | |
| tf | DVI output fall time (20-80%)(4) | 75 | 240 | ps | ||
| tsk(D) | DVI output intra-pair + to ? differential skew(5), see Figure 5-4 | 50 | ps | |||
| tojit | DVI output clock jitter, max.(6) | 150 | ps | |||
| t(STEP) | De-skew trim increment | DKEN = 1 | 350 | ps | ||