4 Pin Configuration and Functions

Figure 4-1 PAP Package,64 Pin HTQFP(Top View)

Table 4-1 Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
INPUT
DATA[23:12]	36?47	I	The upper 12 bits of the 24-bit pixel bus
DATA[23:12]	36?47	I	In 24-bit, single-edge input mode (BSEL = high), this bus inputs the top half of the 24-bit pixel bus. In 12-bit, dual-edge input mode (BSEL = low), these bits are not used to input pixel data. In this mode, the state of DATA[23:16] is input to the I²C register CFG. This allows 8 bits of user configuration data to be read by the graphics controller through the I²C interface (see Section 6.6). Note: All unused data inputs should be tied to GND or V_DD.
DATA[11:0]	50?55, 58?63	I	The lower 12 bits of the 24-bit pixel bus/12-bit pixel bus input
DATA[11:0]	50?55, 58?63	I	In 24-bit, single-edge input mode (BSEL = high), this bus inputs the bottom half of the 24-bit pixel bus. In 12-bit, dual-edge input mode (BSEL = low), this bus inputs 1/2 a pixel (12 bits) at every latch edge (both rising and falling) of the clock.
IDCK– IDCK+	56 57	I	Differential clock input. The TFP410 supports both single-ended and fully differential clock input modes. In the single-ended clock input mode, the IDCK+ input (pin 57) should be connected to the single-ended clock source and the IDCK? input (pin 56) should be tied to GND. In the differential clock input mode, the TFP410 uses the crossover point between the IDCK+ and IDCK– signals as the timing reference for latching incoming data DATA[23:0], DE, HSYNC, and VSYNC. The differential clock input mode is only available in the low signal swing mode.
DE	2	I	Data enable. As defined in DVI 1.0 specification, the DE signal allows the transmitter to encode pixel data or control data on any given input clock cycle. During active video (DE = high), the transmitter encodes pixel data, DATA[23:0]. During the blanking interval (DE = low), the transmitter encodes HSYNC, VSYNC and CTL[3:1].
HSYNC	4	I	Horizontal sync input
VSYNC	5	I	Vertical sync input
A3/DK3 CTL2/A2/DK2 CTL1/A1/DK1	6 7 8	I	The operation of these three multifunction inputs depends on the settings of the ISEL (pin 13) and DKEN (pin 35) inputs. All three inputs support 3.3V CMOS signal levels and contain weak pulldown resistors so that if left unconnected they default to all low.
			When the I²C bus is disabled (ISEL = low) and the de-skew mode is disabled (DKEN = low), pins 7 and 8 become the control inputs, CTL[2:1], which can be used to send additional information across the DVI link during the blanking interval (DE = low). Pin 6 is not used.
			When the I²C bus is disabled (ISEL = low) and the de-skew mode is enabled (DKEN = high), these three inputs become the de-skew inputs DK[3:1], used to adjust the setup and hold times of the pixel data inputs DATA[23:0], relative to the clock input IDCK±.
			When the I²C bus is enabled (ISEL = high), these three inputs become the 3 LSBs of the I²C target address, A[3:1].
CONFIGURATION/PROGRAMMING
MSEN/PO1	11	O	Monitor sense/programmable output 1. The operation of this pin depends on whether the I²C interface is enabled or disabled. This pin has an open-drain output and is only 3.3V tolerant. An external 5kΩ pullup resistor connected to V_DD is required on this pin.
			When I²C is disabled (ISEL = low), a high level indicates a powered on receiver is detected at the differential outputs. A low level indicates a powered on receiver is not detected. This function is only valid in dc-coupled systems.
			When I²C is enabled (ISEL = high), this output is programmable through the I²C interface (see the I²C register descriptions section).
ISEL/ RST	13	I	I²C interface select/I²C RESET (active low, asynchronous)
			If ISEL is high, then the I²C interface is active. Default values for the I²C registers can be found in the see Section 6.6.
			If ISEL is low, then I²C is disabled and the chip configuration is specified by the configuration pins (BSEL, DSEL, EDGE, VREF) and state pins (PD, DKEN).
			If ISEL is brought low and then back high, the I²C state machine is reset. The register values are changed to their default values and are not preserved from before the reset.
BSEL/SCL	15	I	Input bus select/I²C clock input. The operation of this pin depends on whether the I²C interface is enabled or disabled. This pin is only 3.3V tolerant.
			When I²C is disabled (ISEL = low), a high level selects 24-bit input, single-edge input mode. A low level selects 12-bit input, dual-edge input mode.
			When I²C is enabled (ISEL = high), this pin functions as the I²C clock input (see Section 6.6). In this configuration, this pin has an open-drain output that requires an external 5kΩ pullup resistor connected to V_DD.
DSEL/SDA	14	I/O	DSEL/I²C data. The operation of this pin depends on whether the I²C interface is enabled or disabled. This pin is only 3.3V tolerant.
			When I²C is disabled (ISEL = low), this pin is used with BSEL and V_REF to select the single-ended or differential input clock mode (see Table 6-1).
			When I²C is enabled (ISEL = high), this pin functions as the I²C bidirectional data line. In this configuration, this pin has an open-drain output that requires an external 5kΩ pullup resistor connected to V_DD.
EDGE/HTPLG	9	I	Edge select/hot plug input. The operation of this pin depends on whether the I²C interface is enabled or disabled. This input is 3.3V tolerant only.
			When I²C is disabled (ISEL = low), a high level selects the primary latch to occur on the rising edge of the input clock IDCK+. A low level selects the primary latch to occur on the falling edge of the input clock IDCK+. This is the case for both single-ended and differential input clock modes.
			When I²C is enabled (ISEL = high), this pin is used to monitor the hot plug detect signal. When used for hot-plug detection, this pin requires a series 1kΩ resistor.
DKEN	35	I	Data de-skew enable. The de-skew function can be enabled either through I²C or by this pin when I²C is disabled. When de-skew is enabled, the input clock to data setup/hold time can be adjusted in discrete trim increments. The amount of trim per increment is defined by t_(STEP).
			When I²C is disabled (ISEL = low), a high level enables de-skew with the trim increment determined by pins DK[3:1] (see Section 6.4.2). A low level disables de-skew and the default trim setting is used.
			When I²C is enabled (ISEL = high), the value of DKEN and the trim increment are selected through I²C. In this configuration, the DKEN pin should be tied to either GND or V_DD to avoid a floating input.
V_REF	3	I	Input reference voltage. Selects the swing range of the digital data inputs (DATA[23:0], DE, HSYNC, VSYNC, and IDCK±).
			For high-swing 3.3V input signal levels, V_REF should be tied to V_DD.
			For low-swing input signal levels, V_REF should be set to half of the maximum input voltage level. See Section 5.3 for the allowable range for V_REF.
			The desired V_REF voltage level is typically derived using a simple voltage-divider circuit.
PD	10	I	Power down (active low). In the powerdown state, only the digital I/O buffers and I²C interface remain active.
			When I²C is disabled (ISEL = low), a high level selects the normal operating mode. A low level selects the powerdown mode.
			When I²C is enabled (ISEL = high), the power-down state is selected through I²C. In this configuration, the PD pin should be tied to GND.
			Note: The default register value for PD is low, so the device is in powerdown mode when I²C is first enabled or after an I²C RESET.
RESERVED
RESERVED	34	I	This pin is reserved and must be tied to GND for normal operation.
DVI DIFFERENTIAL SIGNAL OUTPUT PINS
TX0+ TX0?	25 24	O	Channel 0 DVI differential output pair. TX0± transmits the 8-bit blue pixel data during active video andHSYNC and VSYNC during the blanking interval.
TX1+ TX1?	28 27	O	Channel 1 DVI differential output pair. TX1± transmits the 8-bit green pixel data during active video and CTL[1] during the blanking interval.
TX2+ TX2?	31 30	O	Channel 2 DVI differential output pair. TX2± transmits the 8-bit red pixel data during active video and CTL[3:2] during the blanking interval.
TXC+ TXC?	22 21	O	DVI differential output clock.
TFADJ	19	I	Full-scale adjust. This pin controls the amplitude of the DVI output voltage swing, determined by the value of the pullup resistor R_TFADJ connected to TV_DD.
POWER AND GROUND PINS
DV_DD	1, 12, 33	Power	Digital power supply. Must be set to 3.3V nominal.
PV_DD	18	Power	PLL power supply. Must be set to 3.3V nominal.
TV_DD	23, 29	Power	Transmitter differential output driver power supply. Must be set to 3.3V nominal.
DGND	16, 48, 64	Ground	Digital ground
PGND	17	Ground	PLL ground
TGND	20, 26, 32	Ground	Transmitter differential output driver ground
NC	49	NC	No connection required. If connected, tie high.

(1) I = input, O = output, NC = no conection, P = power, G = ground