ZHCSUT0D October 2001 – February 2024 TFP410
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD | TDIS | VEN | HEN | DSEL | BSEL | EDGE | PD |
| Bit | Field | Type | Description |
|---|---|---|---|
| 7 | RSVD | R/W | Reserved |
| 6 | TDIS | R/W | This read/write
register contains the T.M.D.S. disable mode 0: T.M.D.S. circuitry enable state is determined by PD. 1: T.M.D.S. circuitry is disabled. |
| 5 | VEN | R/W | This read/write
register contains the vertical sync enable mode. 0: VSYNC input is transmitted as a fixed low 1: VSYNC input is transmitted in its original state |
| 4 | HEN | R/W | This read/write
register contains the horizontal sync enable mode. 0: HSYNC input is transmitted as a fixed low 1: HSYNC input is transmitted in its original state |
| 3 | DSEL | R/W | This read/write register is used in combination with BSEL and VREF to select the single-ended or differential input clock mode. In the high-swing mode, DSEL is a don’t care because IDCK is always single-ended. |
| 2 | BSEL | R/W | This read/write
register contains the input bus select mode. 0: 12-bit operation with dual-edge clock 1: 24-bit operation with single-edge clock |
| 1 | EDGE | R/W | This read/write
register contains the edge select mode. 0: Input data latches to the falling edge of IDCK+ 1: Input data latches to the rising edge of IDCK+ |
| 0 | PD | R/W | This read/write
register contains the power-down mode. 0: Power down (default after RESET) 1: Normal operation |