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ZHCSDU8 July 2015 TDC1011-Q1

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

PW|28
- MPDS364

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

zhcsdu8_oa

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
V_DD	Analog supply voltage, VDD pins	–0.3	6.0	V
V_IO	I/O supply voltage (V_IO must always be lower than or equal to V_DD supply)	–0.3	6.0	V
V_I	Voltage on any analog input pin⁽³⁾	–0.3	V_DD + 0.3	V
V_I	Voltage on any digital input pin⁽³⁾	–0.3	V_IO + 0.3	V
I_I	Input current at any pin		5	mA
T_J	Operating junction temperature	–40	125	°C
T_stg	Storage temperature range	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to ground, unless otherwise specified.

(3) When the input voltage at a pin exceeds the power supplies, the current at that pin must not exceed 5 mA and the voltage (V_I) at that pin must not exceed 6.0 V.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC A100-002⁽¹⁾		±2000	V
		Charged-device model (CDM), per AEC Q100-011	All pins	±500
		Charged-device model (CDM), per AEC Q100-011	Corner pins (1, 14, 15 and 28)	±750

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_DD	Analog supply voltage, VDD pins	2.7	5.5	V
V_IO	Digital supply voltage, (V_IO must always be lower than or equal to V_DD supply)	1.8	V_DD	V
V_I	Voltage on any analog input pin	GND	V_DD	V
V_I	Voltage on any digital input pin	GND	V_IO	V
ƒ_CLKIN	Operating frequency	0.06	16	MHz
T_J	Operating junction temperature	–40	125	°C

6.4 Thermal Information⁽¹⁾

THERMAL METRIC		TDC1011 TSSOP PW (28 PINS)	UNIT
R_θJA	Junction-to-ambient thermal resistance	83.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	29.9
R_θJB	Junction-to-board thermal resistance	40.8
ψ_JT	Junction-to-top characterization parameter	2.4
ψ_JB	Junction-to-board characterization parameter	40.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of the product containing it. T_A = 25°C, V_DD = V_IO = 3.7 V, V_COM = V_CM = V_DD / 2, C_VCOM = 10 nF (unless otherwise noted).

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
TRANSMITTER SIGNAL PATH (TX)
V_OUT(TX)	Output voltage swing	ƒ_out = 1 MHz, R_L = 75 Ω to V_CM	HIGH		V_DD – 0.32		V
V_OUT(TX)	Output voltage swing	ƒ_out = 1 MHz, R_L = 75 Ω to V_CM	LOW		0.32		V
I_OUT(TX)	Output drive current	ƒ_out = 1 MHz, R_L = 75 Ω to V_CM			22		mA_RMS
ƒ_OUT(TX)	Output TX frequency	ƒ_CLKIN = 8 MHz, divide-by-2 (programmable; see Transmitter Signal Path)			4		MHz
RECEIVER SIGNAL PATH (RX)
Δt_STOP	STOP cycle-to-cycle jitter	LNA capacitive feedback, G_PGA = 6 dB, ƒ_IN = 1 MHz, V_IN = 100 mV_PP, C_VCOM = 1 µF and Figure 14			50		ps_RMS
LNA
G_LNA	LNA gain	Capacitive feedback, C_IN = 300 pF, ƒ_IN = 1 MHz, R_L = 100 kΩ to V_CM, C_VCOM = 1 µF			20		dB
en_LNA	LNA input referred noise density	Capacitive feedback, C_IN = 300 pF, ƒ = 1 MHz, V_DD = 3.1 V, V_IN = V_CM, R_L = ∞, C_VCOM = 1 µF			2		nV/√Hz
V_IN(LNA)	Input voltage range	Resistive feedback, R_L = 1 kΩ to V_CM, C_VCOM = 1 µF	HIGH	V_CM + (V_CM – 0.24) / (G_LNA)			V
V_IN(LNA)	Input voltage range	Resistive feedback, R_L = 1 kΩ to V_CM, C_VCOM = 1 µF	LOW	V_CM – (V_CM – 0.24) / (G_LNA)			V
V_OUT(LNA)	Output voltage range	Resistive feedback, R_L= 1 kΩ to V_CM, C_VCOM = 1 µF	HIGH		V_DD – 0.24		V
V_OUT(LNA)	Output voltage range	Resistive feedback, R_L= 1 kΩ to V_CM, C_VCOM = 1 µF	LOW		GND + 0.24		V
SR_LNA	Slew rate⁽⁶⁾	Resistive feedback, R_L = 1 kΩ to V_CM, 100mV step, C_VCOM = 1 µF			9		V/μs
BW_LNA	–3-dB bandwidth	Capacitive feedback, C_IN = 300 pF, R_L= 100 kΩ to V_CM, C_VCOM = 1 µF			5		MHz
V_OS(LNA)	LNA input offset voltage	Resistive mode, V_IN = V_CM, R_L = ∞			±320		µV
VCOM
V_COM	VCOM output voltage	C_VCOM = 1 µF			V_CM		V
	VCOM output error	C_VCOM = 1 µF			0.5%
PGA
V_IN(PGA)	PGA input range	R_L = 100 kΩ to V_CM, C_L = 10 pF to GND	HIGH	V_CM + (V_CM – 0.06) / (G_PGA)			V
V_IN(PGA)	PGA input range	R_L = 100 kΩ to V_CM, C_L = 10 pF to GND	LOW	V_CM – (V_CM – 0.06) / (G_PGA)			V
G_PGAMIN	PGA min gain	DC, R_L = ∞, C_L = 10 pF			0		dB
G_PGAMAX	PGA max gain				21		dB
ΔG_PGA	PGA gain step size				3		dB
G_E(PGA)	PGA gain error	DC, G_PGA = 0 dB, R_L = ∞, C_L = 10 pF			5%
TCG_PGA	PGA gain temperature coefficient	DC, G_PGA = 0 dB, R_L = ∞, C_L = 10 pF			170		ppm/°C
en_PGA	PGA input referred noise density	G_PGA = 21 dB, ƒ = 1 MHz, V_DD = 3.1V, V_IN = V_CM, R_L = ∞, C_VCOM = 1 µF			3.1		nV/√Hz
V_OUT(PGA)	Output range	R_L = 100 kΩ to V_CM, C_L = 10 pF to GND	HIGH		V_DD – 0.06		V
V_OUT(PGA)	Output range	R_L = 100 kΩ to V_CM, C_L = 10 pF to GND	LOW		60		mV
BW_PGA	–3-db bandwidth	G_PGA = 21 dB, R_L = 100 kΩ to V_CM, C_L = 10 pF, C_VCOM = 1 µF			5		MHz
SR_PGA	Slew rate⁽⁶⁾	G_PGA = 21 dB, R_L = 100 kΩ to V_CM, C_L = 10 pF, C_VCOM = 1 µF			12.5		V/µs
ZERO CROSS COMPARATOR
V_OS(COMP)	Input offset voltage⁽⁵⁾	Referred to V_COM			±115		µV
en_COMP	Zero crossing comparator input referred noise⁽⁵⁾	1 MHz			5		nV/√Hz
HYST_COMP	Hysteresis ⁽⁵⁾	Referred to V_COM			-10		mV
THRESHOLD DETECTOR
V_THDET	Threshold level	ECHO_QUAL_THLD = 0h, V_COM referred			–35		mV
V_THDET	Threshold level	ECHO_QUAL_THLD = 7h, V_COM referred			–1.5		V
TEMPERATURE SENSOR INTERFACE⁽¹⁾
T_ERROR	Temperature measurement accuracy	R_REF = 1 kΩ, PT1000 range: –40 to 125°C⁽²⁾			1		°C
T_ERROR	Temperature measurement accuracy	R_REF = 1 kΩ, PT1000 range: –15°C to 85°C⁽²⁾			0.5		°C
	Relative accuracy	R_REF = 1 kΩ, R_RTD1 = R_RTD2 = 1.1 kΩ			0.02		°C_RMS
TG_E	Gain error				5.8		m°C/°C
POWER SUPPLY
I_DD	VDD supply current	Sleep (EN = CLKIN = TRIGGER = low)			0.61		µA
		Continuous receive mode, LNA and PGA bypassed			2.8	3	mA
		Continuous receive mode, LNA and PGA active			6.2	7.5	mA
		Temp. measurement only (PT1000 mode)⁽³⁾			370	400	µA
		Temp. measurement (PT500 mode)⁽⁴⁾			500	540	µA
I_IO	VIO supply sleep current⁽⁵⁾	Sleep (EN = CLKIN = TRIGGER = low)			2		nA
DIGITAL INPUT/OUTPUT CHARACTERISTICS
V_IL	Input logic low threshold					0.2 × V_IO	V
V_IH	Input logic high threshold			0.8 × V_IO			V
V_OL	Output logic low threshold	SDO pin, 100-μA current				0.2	V
		SDO pin, 1.85-mA current				0.4	V
		START and STOP pins, 100-μA current				0.5	V
		START and STOP pins, 1.85-mA current				0.6	V
		ERRB pin, 100-μA current				0.2	V
		ERRB pin, 1.85-mA current				0.4	V
V_OH	Output logic high threshold	SDO pin, 100-μA current		V_IO – 0.2			V
		SDO pin, 1.85-mA current		V_IO – 0.6			V
		START and STOP pins, 100-μA current		V_IO – 0.5			V
		START and STOP pins, 1.85-mA current		V_IO – 0.6			V
		ERRB pin, 0-µA current		V_IO – 0.2			V
I_OMAX	Maximum output current for SDO, START and STOP				1.85		mA

(1) With ideal external components. For more detail see Temp Sensor Measurement section.

(2) PT1000 RTD approximate resistance: 800 Ω ≡ –52°C, 931 Ω ≡ –18°C, 1.10 kΩ ≡ 26°C, 1.33 kΩ ≡ 86°C and 1.48 kΩ ≡ 125°C.

(3) Specified currents include 120μA which flows through the RTD sensor in PT1000 mode (TEMP_RTD_SEL = 0).

(4) Specified currents include 240μA which flows through the RTD sensor in PT500 mode (TEMP_RTD_SEL = 1).

(5) Specified by design.

(6) The slew rate is measured from 10% to 90% and is represented by the average of the rising and falling slew rates.

6.6 Timing Requirements

T_A = 25°C, V_DD = V_IO = 3.7 V and ƒ_SCLK = 1 MHz (unless otherwise noted).

		MIN	NOM	MAX	UNIT
ƒ_SCLK	Serial clock frequency			26	MHz
t₁	High period, SCLK	16			ns
t₂	Low period, SCLK	16			ns
t₃	Set-up time, nCS to SCLK	10			ns
t₄	Set-up time, SDI to SCLK	12			ns
t₅	Hold time, SCLK to SDI	12			ns
t₆	SCLK transition to SDO valid time	16			ns
t₇	Hold time, SCLK transition to nCS rising edge	10			ns
t₈	nCS inactive	17			ns
t₉	Hold time, SCLK transition to nCS falling edge	10			ns
t_r / t_f	Signal rise and fall times⁽¹⁾		1.8		ns

(1) The slew rate is measured from 10% to 90% and is represented by the average of the rising and falling slew rates.

Figure 1. SPI Timing Diagram

6.7 Switching Characteristics

T_A = 25°C, V_DD = V_IO = 3.7 V, ƒ_CLKIN = 8 MHz.

PARAMETER		TEST CONDITIONS	TYP	UNIT
START, STOP, ENABLE, RESET, CLOCKIN, TRIGGER, ERR
PW_START	Pulse width for START signal	TX_FREQ_DIV = 2h, NUM_TX = 1	1	μs
		TX_FREQ_DIV = 2h, NUM_TX = 2	2	μs
		TX_FREQ_DIV = 2h, NUM_TX ≥ 3	3	μs
t_r / t_{f START}	Rise/fall time for START signal	20% to 80%, 20-pF load	0.25	ns
t_r / t_{f STOP}	Rise/fall time for STOP signal	20% to 80%, 20-pF load	0.25	ns
ƒ_CLKIN	Maximum CLKIN input frequency		16	MHz
t_r / t_{f CLKIN}	CLKIN input rise/fall time⁽¹⁾	20% to 80%	10	ns
t_r / t_{f TRIG}	TRIGGER input rise/fall time⁽¹⁾	20% to 80%	10	ns
t_{EN_TRIG}	Enable to trigger wait time⁽¹⁾		50	ns
t_{RES_TRIG}	Reset to trigger wait time⁽¹⁾	TX_FREQ_DIV = 2h (see TX/RX Measurement Sequencing and Timing)	3.05	μs

(1) Specified by design.

6.8 Typical Characteristics

At T_A = 25°C, unless otherwise noted.

V_DD = V_IO = 3.7V	Capacitive Feedback Mode	R_L = 1kΩ

Figure 2. LNA Z_OUT vs Frequency

V_DD = V_IO = 3.1V	Capacitive Feedback Mode	R_L = ∞

Figure 4. LNA Input-referred Noise vs Frequency

V_DD = V_IO = 3.7V	Resistive Feedback Mode	R_L = 1kΩ
V_IN = 100mV	Resistive Feedback Mode	f_IN = 100kHz

Figure 6. LNA Response

V_DD = V_IO = 3.7V	Capacitive Feedback Mode	R_L = 100kΩ
C_IN = 300 pF

Figure 8. LNA Gain vs Frequency

V_DD = V_IO = 5V	LNA Capacitive Feedback Mode	PGA Gain of 6dB
V_IN = 100mV	LNA Capacitive Feedback Mode	f_IN = 1MHz
	(See Figure 14)	Count >= 10000

Figure 10. RX Jitter Histogram

V_DD = V_IO = 3.7V	LNA Capacitive Feedback Mode	PGA Gain of 6dB
V_IN = 100mV	LNA Capacitive Feedback Mode	f_IN = 1MHz
T_A = -40C°	(See Figure 14)	Count >= 10000

Figure 12. RX Jitter Histrogam

V_DD = V_IO = 3.7V	Gain of 21dB	R_L = 1kΩ

Figure 3. PGA Z_OUT vs Frequency

V_DD = V_IO = 3.7V	Gain of 21dB	R_L = ∞

Figure 5. PGA Input-referred Noise vs Frequency

V_DD = V_IO = 3.7V	Gain of 21dB	R_L = 100kΩ
V_IN = 100mV		f_IN = 100kHz

Figure 7. PGA Response

V_DD = V_IO = 3.7V	Gain of 21dB	R_L = 100kΩ

Figure 9. PGA Gain vs Frequency

V_DD = V_IO = 3.7V	LNA Capacitive Feedback Mode	PGA Gain of 6dB
V_IN = 100mV	LNA Capacitive Feedback Mode	f_IN = 1MHz
T_A = 25C°	(See Figure 14)	Count >= 10000

Figure 11. RX Jitter Histogram

V_DD = V_IO = 3.7V	LNA Capacitive Feedback Mode	PGA Gain of 6dB
V_IN = 100mV	LNA Capacitive Feedback Mode	f_IN = 1MHz
T_A = 125C°	(See Figure 14)	Count >= 10000

Figure 13. RX Jitter Histogram