ZHCSDU8 July 2015 TDC1011-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Function Description
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1
TDC1011 Registers
- 8.6.1.1 CONFIG_0 Register (address = 0h) [reset = 45h]
- 8.6.1.2 CONFIG_1 Register (address = 1h) [reset = 40h]
- 8.6.1.3 CONFIG_2 Register (address = 2h) [reset = 0h]
- 8.6.1.4 CONFIG_3 Register (address 3h) [reset = 3h]
- 8.6.1.5 CONFIG_4 Register (address = 4h) [reset = 1Fh]
- 8.6.1.6 TOF_1 Register (address = 5h) [reset = 0h]
- 8.6.1.7 TOF_0 Register (address = 6h) [reset = 0h]
- 8.6.1.8 ERROR_FLAGS Register (address = 7h) [reset = 0h]
- 8.6.1.9 TIMEOUT Register (address = 8h) [reset = 19h]
- 8.6.1.10 CLOCK_RATE Register (address = 9h) [reset = 0h]
- 8.6.1
TDC1011 Registers
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
11 Layout
11.1 Layout Guidelines
- In a 4-layer board design, the recommended layer stack order from top to bottom is: signal, ground, power and signal.
- Bypass capacitors should be placed in close proximity to the VDD and VIO pins.
- The length of the START and STOP traces from the DUT to the stopwatch/MCU should be matched to prevent uneven signal delays. Also, avoid unnecessary via-holes on these traces and keep the routing as short/direct as possible to minimize parasitic capacitance on the PCB.
- Match the length (or resistance) of the traces leading to the RTD sensors. PCB series resistance will be added in series to the RTD sensors.
- Route the SPI signal traces close together. Place a series resistor at the source of SDO (close to the DUT) and series resistors at the sources of SDI, SCLK and CSB (close to the master MCU).
11.2 Layout Example
Figure 57. TDC1011 Board Layout (Capacitive Feedback Mode)