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SLLSFP9 February 2024 TCAN1465-Q1 , TCAN1469-Q1

ADVANCE INFORMATION

封裝選項

機械數據 (封裝 | 引腳)

DMT|14
- MPSS087B
D|14
- MPDS177H

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

sllsfp9_oa

6.8 Timing Requirements

parameters valid across -40℃ ≤ T_J ≤ 150℃ (unless otherwise noted)

		MIN	NOM	MAX	UNIT
SUPPLY
t_PWRUP	Time from V_SUP exceeding4.4V until INH active; see Figure 9-12		2	4	ms
t_UVFLTR	Under voltage detection delay time	3		50	μs
t_UVSLP	Time from an UV_CC and/or UV_IO event to clear before transitioning to sleep or failsafe mode	200		400	ms
MODE CHANGE
t_{MODE_STBY_NOM}	The time it takes for the part to transition to normal mode from standby mode after receiving this command via SPI; see Figure 9-16			70	μs
t_{MODE_NOM_SLP}	The time it takes for the part to transition to sleep mode from normal mode after receiving this command via SPI; see Figure 9-14			200	μs
t_{MODE_SLP_STBY}	Time from UV_CC and UV_IO clearing after INH turns on to RXD pin pulling low; ⁽³⁾ see Figure 9-13			100	μs
t_{MODE_NOM_STBY}	The time it takes for the part to transition to standby mode from normal mode after receiving this command via SPI; see Figure 9-15			70	μs
t_{INH_SLP_STBY}	WUP, LWU or WUF event until INH asserted; see Figure 9-13			100	μs
t_{INH_NOM_SLP}	SPI write to go to sleep from normal mode and INH turns off; see Figure 9-14			50	μs
DEVICE TIMING
t_WAKE	Wake up time from a wake edge on WAKE; standby, selective wake or sleep mode; See Figure 10-16 and Figure 10-17	40			μs
t_{WAKE_INVALID}	WAKE pin pulses shorter than this will be filtered out; See Figure 10-16 and Figure 10-17			10	μs
t_{WK_TIMEOUT}	Bus wake-up timeout value; see Figure 10-14	0.5		2	ms
t_{WK_FILTER}	Bus time to meet filtered bus requirements for wake-up request; 4.75V ≤ VCC ≤ 5.25V; see Figure 10-14	0.5		0.95	μs
t_{WK_WIDTH_MIN}⁽⁴⁾	Minimum WAKE Pin pulse width Register ⁽¹⁾ ⁽²⁾ 11h[3:2] = 00b; see Figure 10-18	10			ms
	Minimum WAKE Pin pulse width Register ⁽¹⁾ ⁽²⁾ 11h[3:2] = 01b; see Figure 10-18	20			ms
	Minimum WAKE Pin pulse width Register ⁽¹⁾ ⁽²⁾ 11h[3:2] = 10b; see Figure 10-18	40			ms
	Minimum WAKE Pin pulse width Register ⁽¹⁾ ⁽²⁾ 11h[3:2] = 11b; see Figure 10-18	80			ms
t_{WK_WIDTH_INVALID}	Maximum WAKE Pin pulse width that is considered invalid ⁽¹⁾ ⁽²⁾ Register 11h[3:2] = 00b; see Figure 10-18			5	ms
	Maximum WAKE Pin pulse width that is considered invalid ⁽¹⁾ ⁽²⁾ Register 11h[3:2] = 01b; see Figure 10-18			10	ms
	Maximum WAKE Pin pulse width that is considered invalid ⁽¹⁾ ⁽²⁾ Register 11h[3:2] = 10b; see Figure 10-18			20	ms
	Maximum WAKE Pin pulse width that is considered invalid ⁽¹⁾ ⁽²⁾ Register 11h[3:2] = 11b; see Figure 10-18			40	ms
t_{WK_WIDTH_MAX}	Maximum WAKE Pin pulse window ⁽¹⁾ Register 11h[1:0] = 00b; see Figure 10-18	750		950	ms
	Maximum WAKE Pin pulse window ⁽¹⁾ Register 11h[1:0] = 01b; see Figure 10-18	1000		1250	ms
	Maximum WAKE Pin pulse window ⁽¹⁾ Register 11h[1:0] = 10b; see Figure 10-18	1500		1875	ms
	Maximum WAKE Pin pulse window ⁽¹⁾ Register 11h[1:0] = 11b; see Figure 10-18	2000		2500	ms
t_SILENCE	Timeout for bus inactivity. Timer is reset and restarted when bus changes from dominant to recessive or vice versa.	0.6		1.2	s
t_INACTIVE	Sleep Wake Error (SWE) timer	3.75		5	min
t_Bias	Time from the start of a dominant-recessive-dominant sequence. Each phase 6 μs until Vsym ≥ 0.1; see Figure 9-9			250	μs
t_{TXD_DTO}	Dominant time out, R_L = 60Ω, C_L = open; see Figure 9-7	1		5	ms
t_TOGGLE	RXD pin toggle timing when programmed after a WUP; see Figure 10-14	5	10	15	μs

(1) This parameter is valid only when register 11h[7:6] = 11b

(2) This is the minimum pulse width for a WAKE pin input that device will detect as a good pulse. Values between the min t_{WK_WIDTH_MIN} and max t_{WK_WIDTH_INVALID} are indeterminate and may or may not be considered valid. This parameter works with t_{WK_WIDTH_MIN} to determine if a WAKE input pulse is valid

(3) Dependent upon V_CC and V_IO being above UV_CC and UV_IO after INH turns on node power.

(4) t_{WK_WIDTH_INVALID} sets this value by using register 11h[3:2]