SLLSFP9 February 2024 TCAN1465-Q1 , TCAN1469-Q1
ADVANCE INFORMATION
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| CAN DRIVER ELECTRICAL CHARACTERISTICS | ||||||
| VO(D) | Bus output voltage (dominant) CANH | See Figure 9-4 VTXD = 0V, RL =45Ω to 65Ω, CL = open, RCM = open | 3 | 4.26 | V | |
| Bus output voltage (dominant) CANL | 0.75 | 2.01 | V | |||
| VO(R) | Bus output voltage (recessive) for CANH and CANL | See Figure 9-1 and Figure 9-4 VTXD = VIO, RL = open (no load), RCM = open | 2 | 2.5 | 3 | V |
| V(DIFF) | Differential voltage | –42 | 42 | V | ||
| VOD(R) | Terminated bus output voltage (recessive) for CANH and CANL | VTXD = VIO, 45Ω ≤ RL ≤ 65Ω, Split termination capacatance 4.7nF | 2.256 | 2.756 | V | |
| VDIFF | Terminated differential voltage rating | VTXD = VIO, 45Ω ≤ RL ≤ 65Ω, Split termination capacatance 4.7nF | –0.05 | 0.05 | V | |
| VOD(D) | Differential output voltage (dominant); extended bus load | See Figure 9-1 and Figure 9-4, VTXD = 0V, 45Ω ≤ RL ≤ 65Ω, CL = open, RCM = open | 1.5 | 3 | V | |
| See Figure 9-1 and Figure 9-4, VTXD = 0V, 45Ω ≤ RL ≤ 70Ω, CL = open, RCM = open | 1.5 | 3.3 | V | |||
| See Figure 9-1 and Figure 9-4, VTXD = 0V, RL = 2.24kΩ, CL = open, RCM = open | 1.5 | 5 | V | |||
| VOD(R) | Differential output voltage (recessive) | See Figure 9-1 and Figure 9-4, VTXD = VIO, RL = 60Ω, CL = open, RCM = open | –120 | 12 | mV | |
| See Figure 9-1 and Figure 9-4, VTXD = VIO, RL = open (no load), CL = open, RCM = open | –50 | 50 | mV | |||
| VO(INACT) | Bus output voltage on CANH with bus biasing inactive (STBY) | See Figure 9-1 and Figure 9-4, VTXD = VIO, RL = open, CL = open, RCM = open | –0.1 | 0.1 | V | |
| Bus output voltage on CANL with bus biasing inactive (STBY) | –0.1 | 0.1 | V | |||
| Bus output voltage on CANH - CANL (recessive) with bus biasing inactive (STBY) | –0.2 | 0.2 | V | |||
| VSYM | Output symmetry (dominant or recessive) (VO(CANH) + VO(CANL))/VCC | See Figure 9-1 and Figure 9-4, 45Ω ≤ RL ≤ 65Ω, CL = open, RCM = open, C1 = 4.7nF, TXD = 250kHz, 1MHz, 2.5MHz | 0.95 | 1.05 | V/V | |
| VSYM_DC | Output symmetry (dominant or recessive) (VCC – VO(CANH) – VO(CANL)) with a frequency that corresponds to the highest bit rate for which the HS-PMA implementation is intended, <1 MHz or <2 Mbit/s | See Figure 9-1 and Figure 9-4, 45Ω ≤ RL ≤ 65Ω, CL = open, RCM = open, C1 = 4.7nF | –300 | 300 | mV | |
| IOS_DOM | Short-circuit steady-state output current, dominant See Figure 9-1 and Figure 9-8 | –3.0V ≤ VCANH ≤ +18.0V, CANL = open, VTXD = 0V | –115 | mA | ||
| –3.0V ≤ VCANL ≤ +18.0 , CANH = open, VTXD = 0V | 115 | mA | ||||
| IOS_REC | Short-circuit steady-state output current, recessive. See Figure 9-1 and Figure 9-8 | –27V ≤ VBUS ≤ +42V, VBUS = CANH = CANL | –5 | 5 | mA | |
| RSE_ACT_REC | Single ended SIC impedance (CANH to common mode bias and CANL to common mode bias) during active recessive drive phase | TXD= 0V, 2V ≤ VO(D) ≤ VCC - 2V if –12V ≤ VO(D) ≤ 12V Use Delta V/ Delta I method(same as used for RSE_PAS_REC/RDIFF_PAS_REC in RX section), no load on bus |
37.5 | 66.5 | ? | |
| RDIFF_ACT_REC | Differential input resistance in active recessive drive phase (CANH to CANL) | 2V ≤ VO(D) ≤ VCC - 2V Duration from TXD= From low-to-high edge to elapse of active recessive drive period (tREC_START), Use Delta V/ Delta I method(same as used for RSE_PAS_REC/RDIFF_PAS_REC in RX section), no load on bus |
75 | 133 | ? | |
| CAN RECEIVER ELECTRICAL CHARACTERISTICS | ||||||
| VITDOM | Receiver dominant state differential input voltage range, bus biasing active | –12V ≤ VCANL ≤ +12V –12V ≤ VCANH ≤ +12V; See Figure 9-5 and Table 10-6 |
0.9 | 8 | V | |
| VITREC | Receiver recessive state differential input voltage range, bus biasing active | –3 | 0.5 | V | ||
| VHYS | Hysteresis voltage for input-threshold, normal and selective wake modes | 135 | mV | |||
| VDIFF_DOM | Receiver dominant state differential input voltage range, bus biasing in-active | 12V ≤ VCANL ≤ +12V –12V ≤ VCANH ≤ +12V; See Figure 9-5 and Table 10-6 |
1.15 | 8 | V | |
| VDIFF_REC | Receiver recessive state differential input voltage range, bus biasing in-active | –3 | 0.4 | V | ||
| VCM | Common mode range: normal and standby mode | –12 | 12 | V | ||
| IIOFF(LKG) | Power-off (unpowered) bus input leakage current | CANH = CANL = 5V, VCC = VIO = Vsup to GND via 0? and 47kΩ resistor | –5 | 5 | μA | |
| CI | Input capacitance to ground (CANH or CANL)(1) | 40 | pF | |||
| CID | Differential input capacitance(1) | 20 | pF | |||
| RDIFF_PAS_REC | Differential input resistance during passive recessive phase | VTXD = VIO, normal mode: –2V ≤ VCANH ≤ +7V; –2V ≤ VCANL ≤ +7V |
12 | 100 | kΩ | |
| RSE_CANH/L | Single ended Input resistance during passive recessive phase (CANH or CANL) | –2V ≤ VCANH ≤ +7V –2V ≤ VCANL ≤ +7V |
6 | 50 | kΩ | |
| RIN(M) | Input resistance matching: [2 x (RIN(CANH - RINCANL)/(RCANH+RINCANL)] | VCANH = VCANL = 5V | –1 | 1 | % | |
| INH OUTPUT TERMINAL (HIGH VOLTAGE OUTPUT) | ||||||
| ΔVH | High-level voltage drop from VSUP to INH | IINH = –6mA | 0.5 | 1 | V | |
| Rpd | Pull-down resistor | Sleep Mode | 7 | 10 | 13 | MΩ |
| WAKE INPUT TERMINAL | ||||||
| VIH | High-level input voltage | Selective wake-up or standby mode, WAKE pin enabled | 4 | V | ||
| VIL | Low-level input voltage | Selective wake-up or standby mode, WAKE pin enabled | 2 | V | ||
| IIL | Low-level input current | WAKE = 1V | 1 | 2 | μA | |
| SDI, SCK, nCS, TXD INPUT TERMINALS | ||||||
| VIH | High-level input voltage | 0.7 | VIO | |||
| VIL | Low-level input voltage | 0.3 | VIO | |||
| IIH | High-level input leakage current | 1.71V ≤ VIO ≤ 5.5V | –1 | 1 | μA | |
| IIL | Low-level input leakage current | Inputs = 0V, 1.71V ≤ VIO ≤ 5.5V | –30 | –2 | μA | |
| CIN | Input capacitance | at 20MHz | 2 | 15 | pF | |
| ILKG(OFF) | Unpowered leakage current | Inputs = 5.5V, VIO = VSUP = 0V | –1 | 0 | 1 | μA |
| Rpu | Pull-up resistor | 250 | 350 | 450 | kΩ | |
| RXD, SDO OUTPUT TERMINALS | ||||||
| VOH | High level output voltage | IOH = -2mA | 0.8 | VIO | ||
| VOL | Low level output voltage | IOL = 2mA | 0.2 | VIO | ||
| ILKG(OFF) | Unpowered leakage current - SDO pin | VnCS = VIO; VO = 0V to VIO | –5 | 5 | μA | |
| RRXD(PU) | RXD pin pull-up resistance | Active during UVSUP and POR conditions and when in Sleep mode | 40 | 60 | 80 | kΩ |
| ILKG(RXD) | RXD current when VIO present and RRXD(PU) enabled | VRXD = VIO; VO = 0V to VIO | –1 | 1 | μA | |
| VRXD = GND; Active during UVSUP and POR conditions and when in Sleep mode | –140 | –20 | μA | |||