The frame detection logic is what enables processing of serial data, or CAN frames, from the CAN bus. The device has selective wake control registers to set up the device to look for a programmed match using either the CAN ID (11 bit or 29 bit), or the CAN ID plus the data frame including data masking. If the detected CAN frame received from the bus matches the configured requirements in the frame detection logic it is called a Wake0Up Frame (WUF).

Before frame detection may be enabled or used the data needed for validation, or match, of the WUF needs to be correctly configured in the device registers. Once the device has been correctly configured to allow frame detection, or selective wake function the SWCFG (Selective Wake Configuration) must be set to load the parameters for WUF for the device. If a valid WUF is detected it is shown via the CANINT flag, including selective wake up.

When frame detection is enabled and the bus is biased to 2.5V from a valid WUP, several other actions may take place as the logic is decoding the CAN frames the device receives on the bus. These include error detection and counting and the indication of reception of a CAN frame via the CAN_SYNC and CAN_SYNC_FD flags.

If a Frame Overflow (FRAME_OVF) occurs while in frame detection mode, it is disabled, clearing the SW_EN bit.

When frame detection is enabled transitioning from a mode where the receiver bias is not on up to four CAN frames for 500kbps and slower data rates and up to eight CAN frames for greater than 500kbps may be ignored by the device until the frame detection is stabilized.

The procedure to correctly configure the device to use frame detection and selective wake up is:

• Write all control registers for frame detection (selective wake), Selective Wake Config 1-4 (Registers 8'h44 through 8'h47), and ID and ID mask (Registers 8'h30 and 8'h40).
• Recommend reading all Selective Wake registers, allowing the software to confirm the device was written and thus configured properly.
• Set Selective Wake Configured (SWCFG) bit to 1b, register 8'4F[7] = 1b.
• Set Selective Wake Enable = 1b, register 8'h10[7] = 1b.

If a SWERR interrupt then occurs from the Frame Overflow flag, the Frame Overflow interrupt needs to be cleared, and then the SWCFG bit must be set again to 1b.