ZHCSJJ3E July 2009 – April 2019 TCA9555
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續）
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
- 9 Detailed Description
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
9.5.1 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin must not exceed the recommended levels for proper operation. Figure 23 shows the simplified schematic of P-Port I/Os.
Figure 23. Simplified Schematic of P-Port I/Os