ZHCS290G September 2009 – June 2018 TCA8418
PRODUCTION DATA.
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the input port register.
The INT output has an open-drain structure and requires a pull-up resistor to VCC depending on the application. If the INT signal is connected back to the processor that provides the SCL signal to the TCA8418, then the INT pin has to be connected to VCC. If not, the INT pin can be connected to VCC.