6.7 Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 19)
|
STANDARD MODE, FAST MODE, FAST MODE PLUS (FM+)
I2C BUS |
UNIT |
| MIN |
MAX |
| tW |
Reset pulse duration |
120(1) |
|
μs |
| tREC |
Reset recovery time |
120(1) |
|
μs |
| tRESET |
Time to reset |
120(1) |
|
μs |
(1) The GPIO debounce circuit uses each GPIO input which passes through a two-stage register circuit. Both registers are clocked by the same clock signal, presumably free-running, with a nominal period of 50 μs. When an input changes state, the new state is clocked into the first stage on one clock transition. On the next same-direction transition, if the input state is still the same as the previously clocked state, the signal is clocked into the second stage, and then on to the remaining circuits. Since the inputs are asynchronous to the clock, it will take anywhere from zero to 50 μs after the input transition to clock the signal into the first stage. Therefore, the total debounce time may be as long as 100 μs. Finally, to account for a slow clock, the spec further guard-banded at 120 μs.