ZHCST08A December 2022 – September 2023 TAS6424R-Q1
PRODUCTION DATA
TDM mode supports 4 or 8 channels of audio data. The TDM mode is automatically selected when the TDM clocks are present. The device can be configured through I2C to use different stereo pairs in the TDM data stream. The TDM mode supports 16-bit, 24-bit, and 32-bit input data lengths.
In TDM mode, SCLK must be 128 x fs or 256 x fs, depending on the TDM slot size. In TDM mode SCLK and MCLK can be connected together. If SCLK and MCLK are connected together or the frequency of SCLK and MCLK is equal, FSYNC must be a minimum 2 MCLK pulses long.
In TDM mode, the SDIN1 pin (pin 15) is used for digital audio data. TI recommends to connect the unused SDIN2 pin (pin 16) to ground.Table 9-1 lists register settings for the TDM channel selection.
| REGISTER SETTING | TDM8 CHANNEL SLOT | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| 0x03 BIT 5 | 0x03 BIT 3 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| 0 | 0 | CH1 | CH2 | CH3 | CH4 | — | — | — | — |
| 1 | 0 | — | — | — | — | CH1 | CH2 | CH3 | CH4 |
| 0 | 1 | CH3 | CH4 | CH1 | CH2 | — | — | — | — |
| 1 | 1 | — | — | — | — | CH3 | CH4 | CH1 | CH2 |
If PBTL mode is programmed for channel 1/2 or channel 3/4 the datasource can be set according to TDM Channel Selection in PBTL Mode.
| REGISTER SETTING | TDM8 CHANNEL SLOT | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 0x03 BIT 5 | 0x03 BIT 3 | 0x21 BIT 6 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| 0 | 0 | 0 | PBTL CH1/2 | — | PBTL CH3/4 | — | — | — | — | — |
| 1 | 0 | 0 | — | — | — | — | PBTL CH1/2 | — | PBTL CH3/4 | — |
| 0 | 0 | 1 | — | PBTL CH1/2 | — | PBTL CH3/4 | — | — | — | — |
| 1 | 0 | 1 | — | — | — | — | — | PBTL CH1/2 | — | PBTL CH3/4 |
| 0 | 1 | 0 | PBTL CH3/4 | — | PBTL CH1/2 | — | — | — | — | — |
| 1 | 1 | 0 | — | — | — | — | PBTL CH3/4 | — | PBTL CH1/2 | — |
| 0 | 1 | 1 | — | PBTL CH3/4 | — | PBTL CH1/2 | — | — | — | — |
| 1 | 1 | 1 | — | — | — | — | — | PBTL CH3/4 | — | PBTL CH1/2 |