ZHCST08A December 2022 – September 2023 TAS6424R-Q1
PRODUCTION DATA
The FAULT pin reports faults and is active low under any of the following conditions:
For all listed faults, the FAULT pin remains asserted after the fault condition is rectified. Deassert the FAULT pin by writing the CLEAR FAULT bit (bit 7) in register 0x21.
The register reports for all fault reports remain asserted until the fault reports are cleared by writing the CLEAR FAULT bit (bit 7) in register 0x21.
Register bits are available to mask fault categories from reporting to the FAULT pin. These bits only mask the setting of the pin and do not affect the register reporting or protection of the device. By default all faults are reported to the pin. See the Register Maps section for a description of the mask settings.
This pin is an open-drain output with an internal 100 kΩ pullup resistor to VDD.