ZHCSMI4 november 2020 TAS6424MS-Q1
PRODUCTION DATA
When any kind of clock error, MCLK-FSYNC or SCLK-FSYNC ratio, or clock halt is detected, the device puts all channels into the Hi-Z state. When all audio clocks are within the expected range, the device automatically returns to the state it was in. See the Electrical Characteristics table for timing requirements.
Figure 9-2 Serial Audio Timing
Figure 9-3 Left-Justified Audio Data Format
Figure 9-4 I2S Audio Data Format
Figure 9-5 TDM8 Audio Data Format