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ZHCSJB8 February 2019 TAS6424M-Q1

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DKQ|56
- MPDS378A

散熱焊盤機械數據 (封裝 | 引腳)

DKQ|56
- PPTD313E

訂購信息

8.5 Electrical Characteristics

Test conditions (unless otherwise noted): T_C = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, R_L = 4 Ω, P_out = 1 W/ch, ƒ = 1 kHz, f_SW = 2.11 MHz, AES17 Filter, default I²C settings, see Figure 79

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OPERATING CURRENT
I_{PVDD_IDLE}	PVDD idle current	All channels playing, no audio input		75	90	mA
I_{VBAT_IDLE}	VBAT idle current	All channels playing, no audio input		90	100	mA
I_{PVDD_STBY}	PVDD standby current	STANDBY Active, VDD = 0 V		0.5	1	μA
I_{VBAT_STBY}	VBAT standby current	STANDBY Active, VDD = 0 V		4	6	μA
I_VDD	VDD supply current	All channels playing, –60-dB signal		15	18	mA
OUTPUT POWER
P_{O_BTL}	Output power per channel, BTL	4 Ω, PVDD = 14.4 V, THD+N = 1%, T_C = 75°C	20	22		W
		4 Ω, PVDD = 14.4 V, THD+N = 10%, T_C = 75°C	25	27
		2 Ω, PVDD = 14.4 V, THD+N = 1%, T_C = 75°C	38	40
		2 Ω, PVDD = 14.4 V, THD+N = 10%, T_C = 75°C	42	45
		4 Ω, PVDD = 18 V, THD+N = 1%, T_C = 75°C	30	33
		4 Ω, PVDD = 18 V, THD+N = 10%, T_C = 75°C	40	45
P_{O_PBTL}	Output power per channel in parallel mode, PBTL	2 Ω, PVDD = 14.4 V, THD+N = 1%, T_C = 75°C	35	40		W
		2 Ω, PVDD = 14.4 V, THD+N = 10%, T_C = 75°C	45	50
		1 Ω, PVDD = 14.4 V, THD+N = 1%, T_C = 75°C	72	80
		1 Ω, PVDD = 14.4 V, THD+N = 10%, T_C = 75°C	80	90
		2 Ω, PVDD = 18 V, THD+N = 1%, T_C = 75°C	60	65
		2 Ω, PVDD = 18 V, THD+N = 10%, T_C = 75°C	75	80
EFF_P	Power efficiency	4 channels operating, 25 W output power/ch, 4 Ω load, PVDD = 14.4 V, T_C = 25°C, including inductor losses⁽¹⁾		86%
AUDIO PERFORMANCE
V_n	Output noise voltage	Zero input, A-weighting, gain level 1, PVDD = 14.4 V		42		μV
		Zero input, A-weighting, gain level 2, PVDD = 14.4 V		55
		Zero input, A-weighting, gain level 3, PVDD = 18 V		67
		Zero input, A-weighting, gain level 4, PVDD = 18 V		85
GAIN	Peak output voltage/dBFS	Gain level 1, Register 0x01, bit 1-0 = 00		7.5		V/FS
		Gain level 2, Register 0x01, bit 1-0 = 01		15
		Gain level 3, Register 0x01, bit 1-0 = 10		21
		Gain level 4, Register 0x01, bit 1-0 = 11		29
Crosstalk	Channel crosstalk	PVDD = 14.4 Vdc + 1 V_RMS, ƒ = 1 kHz		–90		dB
PSRR	Power-supply rejection ratio	PVDD = 14.4 Vdc + 1 V_RMS, ƒ = 1 kHz		75		dB
THD+N	Total harmonic distortion + noise			0.02%
G_CH	Channel-to-channel gain variation		–0.5	0	0.5	dB
LINE OUTPUT PERFORMANCE
V_{n_LINEOUT}	Line output noise voltage	Zero input, A-weighting, channel set to LINE MODE		42		μV
V_{O_LINEOUT}	Line output voltage	0-dB input, channel set to LINE MODE		5.5		V_RMS
THD+N	Line output total harmonic distortion + noise	V_O = 2 V_RMS , channel set to LINE MODE		0.01%
DIGITAL INPUT PINS
V_IH	Input logic level high		70			%VDD
V_IL	Input logic level low				30	%VDD
I_IH	Input logic current, high	V_I = VDD			15	µA
I_IL	Input logic current, low	V_I = 0			–15	µA
PWM OUTPUT STAGE
R_DS(on)	FET drain-to-source resistance	Not including bond wire and package resistance		90		mΩ
OVERVOLTAGE (OV) PROTECTION
V_{PVDD_OV}	PVDD overvoltage shutdown		19.3	20	22	V
V_{PVDD_OV_HYS}	PVDD overvoltage shutdown hysteresis			0.8		V
V_{VBAT_OV}	VBAT overvoltage shutdown		20	21.5	23	V
V_{VBAT_OV_HYS}	VBAT overvoltage shutdown hysteresis			0.6		V
UNDERVOLTAGE (UV) PROTECTION
VBAT_UV	VBAT undervoltage shutdown			4	4.5	V
VBAT_{UV_HYS}	VBAT undervoltage shutdown hysteresis			0.2		V
PVDD_UV	PVDD undervoltage shutdown			4	4.5	V
PVDD_{UV_HYS}	PVDD undervoltage shutdown hysteresis			0.2		V
BYPASS VOLTAGES
V_GVDD	Gate drive bypass pin voltage			7		V
V_AVDD	Analog bypass pin voltage			6		V
V_VCOM	Common bypass pin voltage			2.5		V
V_VREG	Regulator bypass pin voltage			5.5		V
POWER-ON RESET (POR)
V_POR	VDD voltage for POR			2.1	2.7	V
V_{POR_HY}	VDD POR recovery hysteresis voltage			0.5		V
OVERTEMPERATURE (OT) PROTECTION
OTW(i)	Channel overtemperature warning			150		°C
OTSD(i)	Channel overtemperature shutdown			175		°C
OTW	Global junction overtemperature warning	Set by register 0x01 bit 5-6, default value		130		°C
OTSD	Global junction overtemperature shutdown			160		°C
OT_HYS	Overtemperature hysteresis			15		°C
LOAD OVER CURRENT PROTECTION
I_LIM	Overcurrent cycle-by-cycle limit	OC Level 1	4	4.8		A
I_LIM	Overcurrent cycle-by-cycle limit	OC Level 2	6	6.5		A
I_SD	Overcurrent shutdown	OC Level 1, Any short to supply, ground, or other channels		7		A
I_SD	Overcurrent shutdown	OC Level 2, Any short to supply, ground, or other channels		9		A
MUTE MODE
G_MUTE	Output attenuation			100		dB
CLICK AND POP
V_CP	Output click and pop voltage	ITU-R 2k filter, High-Z/MUTE to Play, Play to Mute/High-Z		7		mV
DC OFSET
V_OFFSET	Output offset voltage			2	5	mV
DC DETECT
DC_FAULT	Output DC fault protection			2	2.5	V
DIGITAL OUTPUT PINS
V_OH	Output voltage for logic level high	I = ±2 mA	90			%VDD
V_OL	Output voltage for logic level low	I = ±2 mA			10	%VDD
t_{DELAY_CLIPDET}	Signal delay when output clipping detected				20	μs
LOAD DIAGNOSTICS
S2P	Maximum resistance to detect a short from OUT pins to PVDD				500	Ω
S2G	Maximum resistance to detect a short from OUT pins to ground				200	Ω
SL	Shorted load detection tolerance	Other channels in Hi-Z			±0.5	Ω
OL	Open load	Other channels in Hi-Z	40	70		Ω
T_{DC_DIAG}	DC diagnostic time	All 4 Channels		230		ms
LO	Line output				6	kΩ
T_{LINE_DIAG}	Line output diagnostic time			40		ms
AC_IMP	AC impedance accuracy	Gain linearity, ƒ = 19 kHz, R_L = 2 Ω to 16 Ω,			25%
AC_IMP	AC impedance accuracy	Offset			±0.5	Ω
T_{AC_DIAG}	AC diagnostic time	All 4 Channels		520		ms
I2C_ADDR PINS
t_{I2C_ADDR}	Time delay needed for I²C address set-up			300		μs

Tested with Output Inductor DFEG7030D-3R3M.