ZHCSJT8 May 2019 TAS5806M
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parametric Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3 Feature Description
- 9.4 Device Functional Modes
- 9.5 Programming and Control
- 9.6
Register Maps
- 9.6.1
CONTROL PORT Registers
- 9.6.1.1 RESET_CTRL Register (Offset = 1h) [reset = 0x00]
- 9.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]
- 9.6.1.3 DEVICE_CTRL_2 Register (Offset = 3h) [reset = 0x10]
- 9.6.1.4 I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]
- 9.6.1.5 SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]
- 9.6.1.6 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]
- 9.6.1.7 SDOUT_SEL Register (Offset = 30h) [reset = 0h]
- 9.6.1.8 I2S_CTRL Register (Offset = 31h) [reset = 0x00]
- 9.6.1.9 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]
- 9.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]
- 9.6.1.11 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]
- 9.6.1.12 FS_MON Register (Offset = 37h) [reset = 0x00]
- 9.6.1.13 BCK_MON Register (Offset = 38h) [reset = 0x00]
- 9.6.1.14 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]
- 9.6.1.15 CHANNEL_FORCE_HIZ Register (Offset = 40h) [reset = 0x01]
- 9.6.1.16 DIG_VOL_CTL Register (Offset = 4Ch) [reset = 30h]
- 9.6.1.17 DIG_VOL_CTRL2 Register (Offset = 4Eh) [reset = 0x33]
- 9.6.1.18 DIG_VOL_CTRL3 Register (Offset = 4Fh) [reset = 0x30]
- 9.6.1.19 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]
- 9.6.1.20 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]
- 9.6.1.21 ANA_CTRL Register (Offset = 53h) [reset = 0x00]
- 9.6.1.22 AGAIN Register (Offset = 54h) [reset = 0x00]
- 9.6.1.23 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x00]
- 9.6.1.24 DAC_CTRL Register (Offset = 5Dh) [reset = 0xF8]
- 9.6.1.25 ADR_PIN_CTRL Register (Offset = 60h) [reset = 0h]
- 9.6.1.26 ADR_PIN_CONFIG Register (Offset = 61h) [reset = 0x00]
- 9.6.1.27 DSP_MISC Register (Offset = 66h) [reset = 0h]
- 9.6.1.28 DIE_ID Register (Offset = 67h) [reset = 0h]
- 9.6.1.29 POWER_STATE Register (Offset = 68h) [reset = 0x00]
- 9.6.1.30 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]
- 9.6.1.31 PHASE_CTRL Register (Offset = 6Ah) [reset = 0x00]
- 9.6.1.32 SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]
- 9.6.1.33 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
- 9.6.1.34 SS_CTRL2 Register (Offset = 6Dh) [reset = 0x50]
- 9.6.1.35 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]
- 9.6.1.36 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]
- 9.6.1.37 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]
- 9.6.1.38 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]
- 9.6.1.39 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]
- 9.6.1.40 OT WARNING Register (Offset = 73h) [reset = 0x00]
- 9.6.1.41 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]
- 9.6.1.42 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]
- 9.6.1.43 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]
- 9.6.1.44 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]
- 9.6.1
CONTROL PORT Registers
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
9.3.6 Serial Audio Port - Data Formats and Bit Depths
The device supports industry-standard audio data formats, including standard I2S, left-justified, right-justified and TDM/DSP data. Data formats are selected via Register (P0-R51-D[5:4]). If the high width of LRCK/FS in TDM/DSP mode is less than 8 cycles of SCK, the register (P0-R51-D[3:2]) should set to 01. All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted. All the data formats, word length and clock rate supported by this device are shown in Table 1. The data formats are detailed in Figure 56 through Figure 60. The word length are selected via Register (P0-R51-D[1:0]). The offsets of data are selected via Register (P0-R51-D[7]) and Register (P0-R52-D[7:0]). Default setting is I2S and 24 bit word length.
Figure 56. Left Justified Audio Data Format 
I2S Data Format; L-channel = LOW, R-channel = HIGH
Figure 57. I2S Audio Data Format 
Right Justified Data Format; L-channel = HIGH, R-channel = LOW
Figure 58. Right Justified Audio Data Format 
TDM Data Format with OFFSET = 0
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 59. TDM 1 Audio Data Format 
TDM Data Format with OFFSET = 1
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 60. TDM 2 Audio Data Format