ZHCSDC1D September 2013 – October 2018 TAS5766M , TAS5768M
PRODUCTION DATA.
The TAS576xM offers two power-save modes; standby and power-down.
When a clock error (SCLK, BCLK, and LRCLK) or clock halt is detected, the TAS576xM automatically enters standby mode. The DAC and power amplifier are also powered down. The device can also be placed in standby mode via software command.
When BCLK and LRCLK remain at a low level for more than 1 second, the TAS576xM automatically enters power-down mode. Power-down mode disables the negative charge pump and bias/reference circuit, in addition to those disabled in standby mode. The device can also be placed in power-down mode via I2C command.
When expected Audio clocks (SCLK, BCLK, LRCLK) are applied to the TAS576xM, the device starts its power-up sequence automatically.
| REGISTER | DESCRIPTION |
|---|---|
| Page 0, register 2, D(4) | I2C standby-mode command |
| Page 0, register 2, D(0) | I2C power-down command |
| Page 0, register 2, D(4) and D(0) | I2C power-up sequence command (required after I2C standby or power-down command) |
| Page 0, register 44, D(2:0) | Detection time of BCLK and LRCLK halt |