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ZHCSDC1D September 2013 – October 2018 TAS5766M , TAS5768M

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RMT|48
- MPQF399A
DCA|48
- MPDS044E

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

DCA|48
- PPTD218D

訂購(gòu)信息

7.4.5 PLL Calculation

The TAS576xM has an on-chip PLL with fractional multiplication to generate the clock frequency needed by the audio DAC, Negative Charge Pump, Modulator and Digital Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input (PLLCKIN) supports clock frequencies from 512 kHz to 50 MHz and is register programmable to enable generation of required sampling rates with fine precision.

The PLL is enabled by default. The PLL can be turned on by writing to Page 0, Register 4, D(0). When the PLL is enabled, the PLL output clock PLLCK is given by Equation 1:

Equation 1. TAS5766M TAS5768M Eq1_PLLCK_las965.gif

R = 1, 2, 3,4, … 15, 16
J = 0 4,5,6, … 63 and D = 0000, 0001, 0002, … 9999
K = [J value].[D value]
P 0 1, 2, 3, … 15
R, J, D and P are programmable. J is the integer portion of K (the number to the left of the decimal point) while D is the fraction portion of K (the number to the right of the decimal point, assuming four digits of precision).

Examples:

If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied:

1 MHz ≤ ( PLLCKIN / P ) ≤20 MHz
64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz
1 ≤ J ≤ 63

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied:

6.667 MHz ≤ PLLCLKIN / P ≤ 20 MHz
64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz
4 ≤ J ≤ 11
R = 1

When the PLL is enabled:

fS = (PLLCLKIN × K × R) / (2048 × P)
The value of N is selected so that fS × N = PLLCLKIN x K x R / P is in the allowable range.

Example: MCLK = 12 MHz and fS = 44.1 kHz, (N=2048)
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example: MCLK = 12 MHz and fS = 48.0 kHz, (N=2048)
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Values are written to the registers in Table 6.

Table 6. PLL Registers

DIVIDER	FUNCTION	BITS
PLLE	PLL enable	Page 0, Register 4, D(0)
PPDV	PLL P	Page 0, Register 20, D(3:0)
PJDV	PLL J	Page 0, Register 21, D(5:0)
PDDV	PLL D	Page 0, Register 22, D(5:0)
		Page 0, Register 23, D(7:0)
PRDV	PLL R	Page 0, Register 24, D(3:0)

Table 7. PLL Configuration Recommendations

COLUMN	DESCRIPTION
f_S(kHz)	Sampling frequency
RSCLK	Ration between sampling frequency and SCLK frequency (SCLK frequency = RSCLK x sampling frequency)
SCLK (MHz)	System master clock frequency at SCLK input (pin 22)
PLL VCO (MHz)	PLL VCO frequency as PLLCK
P	One of the PLL coefficients
PLL REF (MHz)	Internal reference clock frequency which is produced by SCLK / P
M = K × R	The final PLL multiplication factor computed from K and R as described in Equation 1
K = J.D	One of the PLL coefficients
R	One of the PLL coefficients
PLL f_S	Ratio between fS and PLL VCO frequency (PLL VCO / fS)
DSP f_S	Ratio between operating clock rate and fS (PLL fS / NMAC)
NMAC	The clock divider value in Table 4
DSP CLK (MHz)	The operating frequency as DSPCK in Clock Generation and PLL
MOD fS	Ratio between DAC operating clock frequency and fS (PLL fS / NDAC)
MOD f(kHz)	DAC operating frequency as DACCK in Clock Generation and PLL
NDAC	DAC clock divider value in Table 4
DOSR	OSR clock divider value in Table DOSR 7 for generating OSRCK in Clock Generation and PLL. DOSR must be chosen so that MOD fS / DOSR = 16 for correct operation.
NCP	NCP (negative charge pump) clock divider value in Table 4
CP f	Negative charge pump clock frequency (fS × MOD fS / NCP)
% Error	Percentage of error between PLL VCO / PLL fS and fS (mismatch error).
	●	This number is typically zero but can be non-zero especially when K is not an integer (D is % Error not zero).
	●	This number may be non-zero only when the TAS576xM acts as a master

Table 8. Recommended Clock Divider Settings for PLL as Master Clock

44.1 kHz
RSCLK	32	64	128	192	256	384	512	768	1024
SCLK (MHz)	1.4112	2.8224	5.6448	8.4672	11.2896	16.9344	22.5792	33.8688	45.1584
PLL VCO (MHz)	90.3168	90.3168	90.3168	90.3168	90.3168	90.3168	90.3168	90.3168	90.3168
P	1	1	1	3	2	3	3	3	3
PLL REF (MHz)	1.4112	2.8224	5.6448	2.8224	5.6448	5.6448	7.526	11.29	15.053
M = K×R	64	32	16	32	16	16	12	8	6
K = J.D	32	16	16	32	16	16	12	8	6
R	2	2	1	1	1	1	1	1	1
PLL f_S	2048	2048	2048	2048	2048	2048	2048	2048	2048
DSP f_S	1024	1024	1024	1024	1024	1024	1024	1024	1024
NMAC	2	2	2	2	2	2	2	2	2
DSP CLK (MHz)	45.1584	45.1584	45.1584	45.1584	45.1584	45.1584	45.1584	45.1584	45.1584
MOD f_S	128	128	128	128	128	128	128	128	128
MOD f (kHz)	5644.8	5644.8	5644.8	5644.8	5644.8	5644.8	5644.8	5644.8	5644.8
NDAC	16	16	16	16	16	16	16	16	16
DOSR	8	8	8	8	8	8	8	8	8
% ERROR	0	0	0	0	0	0	0	0	0
NCP	4	4	4	4	4	4	4	4	4
CP f (kHz)	1411.2	1411.2	1411.2	1411.2	1411.2	1411.2	1411.2	1411.2	1411.2
48kHz
RSCLK	32	64	128	192	256	384	512	768	1024
SCLK (MHz)	1.536	3.072	6.144	9.216	12.288	18.432	24.576	36.864	49.152
PLL VCO (MHz)	98.304	98.304	98.304	98.304	98.304	98.304	98.304	98.304	98.304
P	1	1	1	3	2	3	3	3	3
PLL REF (MHz)	1.536	3.072	6.144	3.072	6.144	6.144	8.192	12.288	16.384
M = K×R	64	32	16	32	16	16	12	8	6
K = J.D	32	16	16	32	16	16	12	8	6
R	2	2	1	1	1	1	1	1	1
PLL fS	2048	2048	2048	2048	2048	2048	2048	2048	2048
DSP f_S	1024	1024	1024	1024	1024	1024	1024	1024	1024
NMAC	2	2	2	2	2	2	2	2	2
DSP CLK (MHz)	49.152	49.152	49.152	49.152	49.152	49.152	49.152	49.152	49.152
MOD f_S	128	128	128	128	128	128	128	128	128
MOD f (kHz)	6144	6144	6144	6144	6144	6144	6144	6144	6144
NDAC	16	16	16	16	16	16	16	16	16
DOSR	8	8	8	8	8	8	8	8	8
% ERROR	0	0	0	0	0	0	0	0	0
NCP	4	4	4	4	4	4	4	4	4
CP f (kHz)	1536	1536	1536	1536	1536	1536	1536	1536	1536