ZHCSBC3F July 2013 – February 2020 TAS5760M
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Digital I/O Pins
- 6.5 Master Clock
- 6.6 Serial Audio Port
- 6.7 Protection Circuitry
- 6.8 Speaker Amplifier in All Modes
- 6.9 Speaker Amplifier in Stereo Bridge Tied Load (BTL) Mode
- 6.10 Speaker Amplifier in Mono Parallel Bridge Tied Load (PBTL) Mode
- 6.11 I²C Control Port
- 6.12 Typical Idle, Mute, Shutdown, Operational Power Consumption
- 6.13 Typical Characteristics (Stereo BTL Mode): fSPK_AMP = 384 kHz
- 6.14 Typical Characteristics (Stereo BTL Mode): fSPK_AMP = 768 kHz
- 6.15 Typical Characteristics (Mono PBTL Mode): fSPK_AMP = 384 kHz
- 6.16 Typical Characteristics (Mono PBTL Mode): fSPK_AMP = 768 kHz
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1
Hardware Control Mode
- 8.4.1.1 Speaker Amplifier Shut Down (SPK_SD Pin)
- 8.4.1.2 Serial Audio Port in Hardware Control Mode
- 8.4.1.3 Soft Clipper Control (SFT_CLIP Pin)
- 8.4.1.4 Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
- 8.4.1.5 Parallel Bridge Tied Load Mode Select (PBTL/SCL Pin)
- 8.4.1.6 Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)
- 8.4.1.7 Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
- 8.4.1.8 Considerations for Setting the Speaker Amplifier Gain Structure
- 8.4.2 Software Control Mode
- 8.4.1
Hardware Control Mode
- 8.5
Register Maps
- 8.5.1 Control Port Registers - Quick Reference
- 8.5.2
Control Port Registers - Detailed Description
- 8.5.2.1 Device Identification Register (0x00)
- 8.5.2.2 Power Control Register (0x01)
- 8.5.2.3 Digital Control Register (0x02)
- 8.5.2.4 Volume Control Configuration Register (0x03)
- 8.5.2.5 Left Channel Volume Control Register (0x04)
- 8.5.2.6 Right Channel Volume Control Register (0x05)
- 8.5.2.7 Analog Control Register (0x06)
- 8.5.2.8 Reserved Register (0x07)
- 8.5.2.9 Fault Configuration and Error Status Register (0x08)
- 8.5.2.10 Reserved Controls (9 / 0x09) - (15 / 0x0F)
- 8.5.2.11 Digital Clipper Control 2 Register (0x10)
- 8.5.2.12 Digital Clipper Control 1 Register (0x11)
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Applications
- 9.2.1 Stereo BTL Using Software Control
- 9.2.2 Stereo BTL Using Software Control, 32-Pin DAP Package Option
- 9.2.3 Stereo BTL Using Hardware Control, 32-Pin DAP Package Option
- 9.2.4 Mono PBTL Using Software Control, 32-Pin DAP Package Option
- 9.2.5 Mono PBTL Using Hardware Control, 32-Pin DAP Package Option
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
8.4.2.5.2 General Operation of the I²C Control Port
The TAS5760M device has a bidirectional I²C interface that is compatible with the Inter IC (I²C) bus protocol and supports both 100-kHz and 400-kHz data transfer rates. This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The control interface is used to program the registers of the device and to read device status.
The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a START condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is HIGH to indicate START and STOP conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 48. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5760M holds SDA LOW during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the HIGH level for the bus.
Figure 48. Typical I²C Sequence There is no limit on the number of bytes that can be transmitted between START and STOP conditions. When the last word transfers, the master generates a STOP condition to release the bus. A generic data transfer sequence is shown in Figure 48.