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ZHCSBC3F July 2013 – February 2020 TAS5760M

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DCA|48
- MPDS044E
DAP|32
- MPDS380A

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

DCA|48
- PPTD094K
DAP|32
- PPTD001K

訂購(gòu)信息

5 Pin Configuration and Functions

DCA PACKAGE

48-PIN TSSOP

TOP VIEW

Pin Functions

PIN		TYPE⁽¹⁾	INTERNAL TERMINATION	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	INTERNAL TERMINATION	DESCRIPTION
AVDD	46	P	-	Power supply for internal analog circuitry
ANA_REF	4	P	-	Connection point for internal reference used by ANA_REG and VCOM filter capacitors
ANA_REG	2	P	-	Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry)
BSTRPA-	39	P	-	Connection point for the SPK_OUTA- bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTA-
BSTRPA+	43	P	-	Connection point for the SPK_OUTA+ bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTA
BSTRPB-	38	P	-	Connection point for the SPK_OUTB- bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTB-
BSTRPB+	34	P	-	Connection point for the SPK_OUTB+ bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTB+
DGND	17	G	-	Ground for digital circuitry (NOTE: This pin should be connected to the system ground)
DVDD	9	P	-	Power supply for the internal digital circuitry
FREQ/SDA	7	DI	Weak Pull-Down	Dual function pin that functions as an I²C data input pin in I²C Control Mode or as a Frequency Select terminal when in Hardware Control Mode.
GGND	47	G	-	Ground for gate drive circuitry (this terminal should be connected to the system ground)
GVDD_REG	48	P	-	Voltage regulator derived from PVDD supply (NOTE: This pin is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry)
LRCK	16	DI	Weak Pull-Down	Word select clock for the digital signal that is active on the serial port's input data line
MCLK	13	DI	Weak Pull-Down	Master Clock used for internal clock tree, sub-circuit/state machine, and Serial Audio Port clocking
NC	18-31	-	-	Not connected inside the device (all "no connect" pins should be connected to ground for best thermal performance, however they can be used as routing channels if required.)
PBTL/SCL	8	DI	Weak Pull-Down	Dual function pin that functions as an I²C clock input terminal in I²C Control Mode or configures the device to operate in pre-filter Parallel Bridge Tied Load (PBTL) mode when in Hardware Control Mode
PGND	36, 41	G	-	Ground for power device circuitry (NOTE: This terminal should be connected to the system ground)
PVDD	32, 33, 44, 45	P	-	Power Supply for internal power circuitry
SCLK	14	DI	Weak Pull-Down	Bit clock for the digital signal that is active on the serial data port's input data line
SDIN	15	DI	Weak Pull-Down	Data line to the serial data port
SFT_CLIP	1	AI	-	sets the maximum output voltage before clipping
SPK_FAULT	5	DO	-	Speaker amplifier fault terminal, which is pulled LOW when an internal fault occurs
SPK_GAIN0	10	DI	Weak Pull-Down	Adjusts the LSB of the multi-bit gain of the speaker amplifier
SPK_GAIN1	11	DI	Weak Pull-Down	Adjusts the MSB of the multi-bit gain of the speaker amplifier
SPK_SLEEP/ADR	12	DI	Weak Pull-Up	In Hardware Control Mode, places the speaker amplifier in sleep mode. In Software Control Mode, is used to determine the I²C Address of the device
SPK_OUTA-	40	AO	-	Negative pin for differential speaker amplifier output A
SPK_OUTA+	42	AO	-	Positive pin for differential speaker amplifier output A
SPK_OUTB-	37	AO	-	Negative pin for differential speaker amplifier output B
SPK_OUTB+	35	AO	-	Positive pin for differential speaker amplifier output B
SPK_SD	6	AO	-	Places the speaker amplifier in shutdown
VCOM	3	P	-	Bias voltage for internal PWM conversion block
PowerPAD™	-	G	-	Provides both electrical and thermal connection from the device to the board. A matching ground pad must be provided on the PCB and the device connected to it via solder. For proper electrical operation, this ground pad must be connected to the system ground.

DAP PACKAGE

32-PIN TSSOP

TOP VIEW

Pin Functions

PIN		TYPE⁽¹⁾	INTERNAL TERMINATION	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	INTERNAL TERMINATION	DESCRIPTION
AVDD	1	P	-	Power supply for internal analog circuitry
ANA_REF	5	P	-	Connection point for internal reference used by ANA_REG and VCOM filter capacitors
ANA_REG	3	P	-	Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry)
BSTRPA–	25	P	-	Connection point for the SPK_OUTA– bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTA–
BSTRPA+	30	P	-	Connection point for the SPK_OUTA+ bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTA
BSTRPB–	24	P	-	Connection point for the SPK_OUTB- bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTB-
BSTRPB+	19	P	-	Connection point for the SPK_OUTB+ bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTB+
DGND	18	G	-	Ground for digital circuitry (NOTE: This terminal should be connected to the system ground)
DVDD	10	P	-	Power supply for the internal digital circuitry
FREQ/SDA	8	DI	Weak Pull-Down	Dual function terminal that functions as an I²C data input terminal in I²C Control Mode or as a Frequency Select terminal when in Hardware Control Mode.
GGND	31	G	-	Ground for gate drive circuitry (this terminal should be connected to the system ground)
GVDD_REG	32	P	-	Voltage regulator derived from PVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry)
LRCK	17	DI	Weak Pull-Down	Word select clock for the digital signal that is active on the serial port's input data line
MCLK	14	DI	Weak Pull-Down	Master Clock used for internal clock tree, sub-circuit/state machine, and Serial Audio Port clocking
PBTL/SCL	9	DI	Weak Pull-Down	Dual function terminal that functions as an I²C clock input terminal in I²C Control Mode or configures the device to operate in pre-filter Parallel Bridge Tied Load (PBTL) mode when in Hardware Control Mode
PGND	22, 27	G	-	Ground for power device circuitry (NOTE: This terminal should be connected to the system ground)
PVDD	21, 28	P	-	Power Supply for internal power circuitry
SCLK	15	DI	Weak Pull-Down	Bit clock for the digital signal that is active on the serial data port's input data line
SDIN	16	DI	Weak Pull-Down	Data line to the serial data port
SFT_CLIP	2	AI	-	Sets the maximum output voltage before clipping
SPK_FAULT	6	DO	Open Drain	Fault terminal, which is pulled LOW when an internal fault occurs
SPK_GAIN0	11	DI	Weak Pull-Down	Adjusts the LSB of the multi-bit gain of the speaker amplifier
SPK_GAIN1	12	DI	Weak Pull-Down	Adjusts the MSB of the multi-bit gain of the speaker amplifier
SPK_SLEEP/ADR	13	DI	Weak Pull-Up	Places the speaker amplifier in mute
SPK_OUTA–	26	AO	-	Negative terminal for differential speaker amplifier output
SPK_OUTA+	29	AO	-	Positive terminal for differential speaker amplifier output
SPK_OUTB–	23	AO	-	Negative terminal for differential speaker amplifier output B
SPK_OUTB+	20	AO	-	Positive terminal for differential speaker amplifier output B
SPK_SD	7	DI	-	Places the device in shutdown when pulled LOW
VCOM	4	P	-	Bias voltage for internal PWM conversion block
PowerPAD™	-	G	-	Provides both electrical and thermal connection from the device to the board. A matching ground pad must be provided on the PCB and the device connected to it via solder.

(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, P = Power, G = Ground (0 V)