ZHCSI79B March 2016 – May 2018 TAS5751M
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Characteristics
- 6.5 Electrical Characteristics
- 6.6 Speaker Amplifier Characteristics
- 6.7 Protection Characteristics
- 6.8 Master Clock Characteristics
- 6.9 I²C Interface Timing Requirements
- 6.10 Serial Audio Port Timing Requirements
- 6.11 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Audio Signal Processing Overview
- 7.4 Feature Description
- 7.5 Device Functional Modes
- 7.6 Programming
- 7.7
Register Maps
- 7.7.1 Register Summary
- 7.7.2
Detailed Register Descriptions
- 7.7.2.1 Clock Control Register (0x00)
- 7.7.2.2 Device ID Register (0x01)
- 7.7.2.3 Error Status Register (0x02)
- 7.7.2.4 System Control Register 1 (0x03)
- 7.7.2.5 Serial Data Interface Register (0x04)
- 7.7.2.6 System Control Register 2 (0x05)
- 7.7.2.7 Soft Mute Register (0x06)
- 7.7.2.8 Volume Registers (0x07, 0x08, 0x09)
- 7.7.2.9 Volume Configuration Register (0x0E)
- 7.7.2.10 Modulation Limit Register (0x10)
- 7.7.2.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
- 7.7.2.12 PWM Shutdown Group Register (0x19)
- 7.7.2.13 Start/Stop Period Register (0x1A)
- 7.7.2.14 Oscillator Trim Register (0x1B)
- 7.7.2.15 BKND_ERR Register (0x1C)
- 7.7.2.16 Input Multiplexer Register (0x20)
- 7.7.2.17 PWM Output MUX Register (0x25)
- 7.7.2.18 AGL Control Register (0x46)
- 7.7.2.19 PWM Switching Rate Control Register (0x4F)
- 7.7.2.20 Bank Switch and EQ Control (0x50)
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1
Stereo Bridge Tied Load Application
- 8.2.1.1 Design Requirements
- 8.2.1.2 Detailed Design Procedure
- 8.2.1.3 Application Performance Plots
- 8.2.2 Mono Parallel Bridge Tied Load Application
- 8.2.1
Stereo Bridge Tied Load Application
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.6.3 26-Bit 3.23 Number Format
All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23 numbers mean that the binary point has 3 bits to the left and 23 bits to the right. This is shown in Figure 64.
Figure 64. 3.23 Format The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 64. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number. In the case every bit must be inverted, a 1 added to the result, and then the weighting shown in Figure 65 applies to obtain the magnitude of the negative number.
Figure 65. Conversion Weighting Factors—3.23 Format to Floating Point Gain coefficients, entered via the I²C bus, must be entered as 32-bit binary numbers. The format of the 32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 66.
Figure 66. Alignment of 3.23 Coefficient in 32-Bit I²C Word Table 3. Sample Calculation for 3.23 Format
| db | Linear | Decimal | Hex (3.23 Format) |
|---|---|---|---|
| 0 | 1 | 8,388,608 | 80 0000 |
| 5 | 1.77 | 14,917,288 | 00E3 9EA8 |
| –5 | 0.56 | 4,717,260 | 0047 FACC |
| X | L = 10(X / 20) | D = 8,388,608 × L | H = dec2hex (D, 8) |
Table 4. Sample Calculation for 9.17 Format
| db | Linear | Decimal | Hex (9.17 Format) |
|---|---|---|---|
| 0 | 1 | 131,072 | 2 0000 |
| 5 | 1.77 | 231,997 | 3 8A3D |
| –5 | 0.56 | 73,400 | 1 1EB8 |
| X | L = 10(X / 20) | D = 131,072 × L | H = dec2hex (D, 8) |