ZHCSI79B March 2016 – May 2018 TAS5751M
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Characteristics
- 6.5 Electrical Characteristics
- 6.6 Speaker Amplifier Characteristics
- 6.7 Protection Characteristics
- 6.8 Master Clock Characteristics
- 6.9 I²C Interface Timing Requirements
- 6.10 Serial Audio Port Timing Requirements
- 6.11 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Audio Signal Processing Overview
- 7.4 Feature Description
- 7.5 Device Functional Modes
- 7.6 Programming
- 7.7
Register Maps
- 7.7.1 Register Summary
- 7.7.2
Detailed Register Descriptions
- 7.7.2.1 Clock Control Register (0x00)
- 7.7.2.2 Device ID Register (0x01)
- 7.7.2.3 Error Status Register (0x02)
- 7.7.2.4 System Control Register 1 (0x03)
- 7.7.2.5 Serial Data Interface Register (0x04)
- 7.7.2.6 System Control Register 2 (0x05)
- 7.7.2.7 Soft Mute Register (0x06)
- 7.7.2.8 Volume Registers (0x07, 0x08, 0x09)
- 7.7.2.9 Volume Configuration Register (0x0E)
- 7.7.2.10 Modulation Limit Register (0x10)
- 7.7.2.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
- 7.7.2.12 PWM Shutdown Group Register (0x19)
- 7.7.2.13 Start/Stop Period Register (0x1A)
- 7.7.2.14 Oscillator Trim Register (0x1B)
- 7.7.2.15 BKND_ERR Register (0x1C)
- 7.7.2.16 Input Multiplexer Register (0x20)
- 7.7.2.17 PWM Output MUX Register (0x25)
- 7.7.2.18 AGL Control Register (0x46)
- 7.7.2.19 PWM Switching Rate Control Register (0x4F)
- 7.7.2.20 Bank Switch and EQ Control (0x50)
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1
Stereo Bridge Tied Load Application
- 8.2.1.1 Design Requirements
- 8.2.1.2 Detailed Design Procedure
- 8.2.1.3 Application Performance Plots
- 8.2.2 Mono Parallel Bridge Tied Load Application
- 8.2.1
Stereo Bridge Tied Load Application
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.6.1.6 Single-Byte Read
As shown in Figure 53, a single-byte data-read transfer begins with the master device transmitting a start condition, followed by the I²C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5751M address and the read/write bit, TAS5751M device responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5751M address and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the TAS5751M device again responds with an acknowledge bit. Next, the TAS5751M device transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read transfer.
Figure 53. Single-Byte Read Transfer