ZHCSEH3B December 2015 – September 2018 TAS5411-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3 Feature Description
- 9.4 Device Functional Modes
- 9.5 Register Maps
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
7.6 Timing Requirements for I2C Interface Signals
over recommended operating conditions (unless otherwise noted)| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| f(SCL) | SCL clock frequency | 400 | kHz | ||
| tr | Rise time for both SDA and SCL signals | 300 | ns | ||
| tf | Fall time for both SDA and SCL signals | 300 | ns | ||
| tw(H) | SCL pulse duration, high | 0.6 | μs | ||
| tw(L) | SCL pulse duration, low | 1.3 | μs | ||
| tsu(2) | Setup time for START condition | 0.6 | μs | ||
| th(2) | START condition hold time before generation of first clock pulse | 0.6 | μs | ||
| tsu(1) | Data setup time | 100 | ns | ||
| th(1) | Data hold time | 0(1) | ns | ||
| tsu(3) | Setup time for STOP condition | 0.6 | μs | ||
| C(B) | Load capacitance for each bus line | 400 | pF | ||
(1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL.
Figure 1. SCL and SDA Timing 
Figure 2. Timing for Start and Stop Conditions