ZHCSFY2B August 2015 – February 2019 TAS2555
PRODUCTION DATA.
Audio data is transferred between the host processor and the TAS2555 device via the digital audio data serial interface, or audio bus. The audio bus on this device is flexible, including left or right-justified data options, support for I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple devices within a system directly.
The audio bus of the TAS2555 device can be configured for left or right-justified, I2S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring Registers B0_P1_R1_D[4:3] and B0_P1_R2_D[4:3] for ASI1 and Registers B0_P1_R21_D[4:3] and B0_P1_R22_d[4:3] . In addition, the word clock and bit clock can be independently configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. This signal can be programmed to generate variable clock pulses by controlling the bit-clock multiply-divide factor in Registers 0x08 through 0x10. The number of bit-clock pulses in a frame may require adjustment to accommodate various word-lengths as well as to support the case when multiple TAS2555 devices may share the same audio bus.
The TAS2555 device also includes a feature to offset the position of start of data transfer with respect to the word-clock. This offset is in number of bit-clocks and is programmed in Register 0x06.
To place the DOUT line into a Hi-Z (3-state) condition during all bit clocks when valid data is not being sent, set Register B0_P1_R1_D[0] = 1 for ASI1 and Register B0_P1_R21[0] = 1. By combining this capability with the ability to program what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished. This enables the use of multiple devices on a single audio serial data bus. When the audio serial data bus is powered down while configured in master mode, the terminals associated with the interface are put into a Hi-Z output state.