ZHCSGI2E july 2017 – july 2023 TAS2505-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 I2S/LJF/RJF Timing in Master Mode
- 6.7 I2S/LJF/RJF Timing in Slave Mode
- 6.8 DSP Timing in Master Mode
- 6.9 DSP Timing in Slave Mode
- 6.10 I2C Interface Timing
- 6.11 SPI Interface Timing
- 6.12 Typical Characteristics
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Register Map
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
6.11 SPI Interface Timing
At 25°C, DVDD = 1.8V
| PARAMETER | TEST CONDITION | IOVDD=1.8V | IOVDD=3.3V | UNIT | |||||
|---|---|---|---|---|---|---|---|---|---|
| MIN | TYP | MAX | MIN | TYP | MAX | ||||
| tsck | SCLK period (1) | 100 | 50 | ns | |||||
| tsckh | SCLK pulse width High | 50 | 25 | ns | |||||
| tsckl | SCLK pulse width Low | 50 | 25 | ns | |||||
| tlead | Enable lead time | 30 | 20 | ns | |||||
| tlag | Enable lag time | 30 | 20 | ns | |||||
| td | Sequential transfer delay | 40 | 20 | ns | |||||
| ta | Slave DOUT access time | 40 | 40 | ns | |||||
| tdis | Slave DOUT disable time | 40 | 40 | ns | |||||
| tsu | DIN data setup time | 15 | 15 | ns | |||||
| thi | DIN data hold time | 15 | 10 | ns | |||||
| tv;DOUT | DOUT data valid time | 25 | 18 | ns | |||||
| tr | SCLK rise time | 4 | 4 | ns | |||||
| tf | SCLK fall time | 4 | 4 | ns | |||||
(1) These parameters are based on characterization and are not tested in production.
Figure 6-1 I2S/LJF/RJF Timing in Master Mode
Figure 6-2 I2S/LJF/RJF Timing in Slave Mode
Figure 6-3 DSP Timing in Master Mode
Figure 6-4 DSP Timing in Slave Mode
Figure 6-5 I2C Interface Timing
Figure 6-6 SPI Interface Timing Diagram