ZHCSGI2E july 2017 – july 2023 TAS2505-Q1
PRODUCTION DATA
Table 8-1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | ||
|---|---|---|---|---|---|---|---|---|
| PIN FUNCTION | MCLK | BCLK | WCLK | DIN | GPIO /DOUT | SCLK | MISO | |
| A | PLL Input | S(2) | S(3) | E | S(4) | |||
| B | Codec Clock Input | S(2),D(5) | S(3) | S(4) | ||||
| C | I2S BCLK input | S(3),D | ||||||
| D | I2S BCLK output | E(1) | ||||||
| E | I2S WCLK input | E, D | ||||||
| F | I2S WCLK output | E | ||||||
| G | I2S DIN | E, D | ||||||
| I | General-Purpose Output I | E | ||||||
| I | General-Purpose Output II | E | ||||||
| J | General-Purpose Input I | E | ||||||
| J | General-Purpose Input II | E | ||||||
| J | General-Purpose Input III | E | ||||||
| K | INT1 output | E | E | |||||
| L | INT2 output | E | E | |||||
| M | Secondary I2S BCLK input | E | E | |||||
| N | Secondary I2S WCLK input | E | E | |||||
| O | Secondary I2S DIN | E | E | |||||
| P | Secondary I2S BCLK OUT | E | E | |||||
| Q | Secondary I2S WCLK OUT | E | E | |||||
| R | Secondary I2S DOUT | E | ||||||
| S | Aux Clock Output | E | E |