ZHCSGI2E july 2017 – july 2023 TAS2505-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 I2S/LJF/RJF Timing in Master Mode
- 6.7 I2S/LJF/RJF Timing in Slave Mode
- 6.8 DSP Timing in Master Mode
- 6.9 DSP Timing in Slave Mode
- 6.10 I2C Interface Timing
- 6.11 SPI Interface Timing
- 6.12 Typical Characteristics
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Register Map
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGE|24
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGE|24
訂購(gòu)信息
5 Pin Configuration and Functions
Figure 5-1 RGE Package24-Pin VQFNTop ViewTable 5-1 Pin Functions
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | SPI_SEL | I | Selects between SPI and I2C digital interface modes; (1 = SPI mode) (0 = I2C mode) |
| 2 | RST | I | Reset for logic, state machines, and digital filters; asserted LOW. |
| 3 | AINL | I | Analog single-ended line left input |
| 4 | AINR | I | Analog single-ended line right input |
| 5 | NC | O | No Connect (Leave unconnected) |
| 6 | AVSS | GND | Analog Ground, 0 V |
| 7 | AVDD | PWR | Analog Core Supply Voltage, 1.5 V to 1.95 V, tied internally to the LDO output |
| 8 | LDO_SEL | I | Select Pin for LDO; ties to either SPKVDD or SPKVSS |
| 9 | SPKM | O | Class-D speaker driver inverting output |
| 10 | SPKVDD | PWR | Class-D speaker driver power supply |
| 11 | SPKVSS | PWR | Class-D speaker driver power supply ground supply |
| 12 | SPKP | O | Class-D speaker driver noninverting output |
| 13 | DIN | I | Audio Serial Data Bus Input Data |
| 14 | WCLK | I/O | Audio Serial Data Bus Word Clock |
| 15 | BCLK | I/O | Audio Serial Data Bus Bit Clock |
| 16 | MCLK | I | Master CLK Input / Reference CLK for CLK Multiplier - PLL (On startup PLLCLK = CLKIN) |
| 17 | MISO | O | SPI Serial Data Output |
| 18 | GPIO/DOUT | I/O/Z | GPIO / Audio Serial Bus Output |
| 19 | SCL/SSZ | I | Either I2C Input Serial Clock or SPI Chip Select Signal depending on SPI_SEL state |
| 20 | SDA/MOSI | I | Either I2C Serial Data Input or SPI Serial Data Input depending on SPI_SEL state. |
| 21 | SCLK | I | Serial clock for SPI interface |
| 22 | IOVDD | PWR | I/O Power Supply, 1.1 V to 3.6 V |
| 23 | DVDD | PWR | Digital Power Supply, 1.65 V to 1.95 V |
| 24 | DVSS | GND | Digital Ground, 0 V |
(1) I = Input, O = Output, GND = Ground, PWR = Power, Z = High
Impedance