ZHCSL98G October 2009 – September 2021 SN74LVC1G74
PRODUCTION DATA
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
The 330 Ω resistor and 22 pF capacitor shown in Figure 9-1 produce enough delay to meet the hold time requirement of the D input. To calculate the delay for a particular RC combination, use Equation 1. The delay with this RC combination is 5.03 ns
To ensure proper operation, check that the transition time of the RC circuit meets the transition time requirements of the device inputs listed in the Recommended Operating Conditions table. Transition time for an RC can be approximated with Equation 2.