SCES414P November 2002 – November 2016 SN74LVC1G57
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DRY|6
訂購信息
1 Features
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Supports Down Translation to VCC
- Max tpd of 6.3 ns at 3.3 V
- Schmitt-Triggered Inputs
- Low Power Consumption, 10-µA Maximum ICC
- ±24-mA Output Drive at 3.3 V
- Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- Available in the Texas Instruments
NanoFree™ Package
2 Applications
- Active Noise Cancellation (ANC)
- Barcode Scanners
- Blood Pressure Monitors
- CPAP Machines
- Cable Solutions
- Embedded PCs
- Field Transmitter: Temperature or Pressure Sensors
- HVAC: Heating, Ventilating, and Air Conditioning
- TVs: High-Definition (HDTV), LCD, and Digital
- Video Communications Systems
3 Description
The SN74LVC1G57 device features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND.
This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
Device Information(1)
| DEVICE NAME | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| SN74LVC1G57DBV | SOT-23 (6) | 2.90 mm × 1.60 mm |
| SN74LVC1G57DCK | SC70 (6) | 2.00 mm × 1.25 mm |
| SN74LVC1G57DRL | SOT (6) | 1.60 mm × 1.20 mm |
| SN74LVC1G57DRY | SON (6) | 1.45 mm × 1.00 mm |
| SN74LVC1G57DSF | SON (6) | 1.00 mm × 1.00 mm |
| SN74LVC1G57YZP | DSBGA (6) | 1.41 mm × 0.91 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
Logic Diagram (Positive Logic)
