ZHCSWI5F August 2003 – October 2024 SN74LV4053A-Q1
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
Figure 4-1 D, PW or DYY Package, 16-Pin
TSSOP, SOT-23-THIN (Top View)| PIN | TYPE(2) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| 2Y1 | 1 | I(1) | Input to mux 2 |
| 2Y0 | 2 | I(1) | Input to mux 2 |
| 3Y1 | 3 | I(1) | Input to mux 3 |
| 3-COM | 4 | O(1) | Output of mux 3 |
| 3Y0 | 5 | I(1) | Input to mux 3 |
| INH | 6 | I | Enables the outputs of the device. Logic low level with turn the outputs on, high level will turn them off. |
| GND | 7 | - | Ground |
| GND | 8 | - | Ground |
| C | 9 | I | Selector line for outputs (see Section 7.2 for specific information) |
| B | 10 | I | Selector line for outputs (see Section 7.2 for specific information) |
| A | 11 | I | Selector line for outputs (see Section 7.2 for specific information) |
| 1Y0 | 12 | I(1) | Input to mux 1 |
| 1Y1 | 13 | I(1) | Input to mux 1 |
| 1-COM | 14 | O(1) | Output of mux 1 |
| 2-COM | 15 | O(1) | Output of mux 2 |
| VCC | 16 | I | Device power input |