ZHCSHF0L March   2002  – January 2018 SN74AUC1G126

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

1. 1 特性
2. 2 應(yīng)用
3. 3 說明
   1.     Device Images
      1.      邏輯圖（正邏輯）
4. 4 修訂歷史記錄
5. 5 Pin Configuration and Functions
   1.     Pin Functions
6. 6 Specifications
   1. 6.1 Absolute Maximum Ratings
   2. 6.2 ESD Ratings
   3. 6.3 Recommended Operating Conditions
   4. 6.4 Thermal Information
   5. 6.5 Electrical Characteristics
   6. 6.6 Switching Characteristics: CL = 15 pF
   7. 6.7 Switching Characteristics: CL = 30 pF
   8. 6.8 Operating Characteristics
7. 7 Typical Characteristics
8. 8 Parameter Measurement Information
9. 9 Detailed Description
   1. 9.1 Overview
   2. 9.2 Functional Block Diagram
   3. 9.3 Feature Description
      1. 9.3.1 Balanced CMOS Push-Pull Outputs
      2. 9.3.2 Standard CMOS Inputs
      3. 9.3.3 Negative Clamping Diodes
      4. 9.3.4 Special Features
         1. 9.3.4.1 Partial Power Down (Ioff)
         2. 9.3.4.2 Overvoltage Tolerant Inputs
         3. 9.3.4.3 Output Enable
   4. 9.4 Device Functional Modes
10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
       1. 10.2.1 Design Requirements
       2. 10.2.2 Detailed Design Procedure
       3. 10.2.3 Application Curve
11. 11Power Supply Recommendations
12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
13. 13器件和文檔支持
    1. 13.1 Documentation Support
       1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 商標(biāo)
    5. 13.5 靜電放電警告
    6. 13.6 Glossary
14. 14機(jī)械、封裝和可訂購信息