ZHCSBP5C september 2013 – october 2020 SN65DSI86
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Description (continued)
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1 Reset Implementation
- 8.4.2 Power-Up Sequence
- 8.4.3 Power Down Sequence
- 8.4.4 Display Serial Interface (DSI)
- 8.4.5
DisplayPort
- 8.4.5.1 HPD (Hot Plug/Unplug Detection)
- 8.4.5.2 AUX_CH
- 8.4.5.3 I2C-Over-AUX
- 8.4.5.4 DisplayPort PLL
- 8.4.5.5 DP Output VOD and Pre-emphasis Settings
- 8.4.5.6 DP Main Link Configurability
- 8.4.5.7 DP Main Link Training
- 8.4.5.8 Panel Size vs DP Configuration
- 8.4.5.9 Panel Self Refresh (PSR)
- 8.4.5.10 Secondary Data Packet (SDP)
- 8.4.5.11 Color Bar Generator
- 8.4.5.12 DP Pattern
- 8.4.5.13 BPP Conversion
- 8.5 Programming
- 8.6 Register Map
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
6 Pin Configuration and Functions
Table 6-1 Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| ADDR | A1 | CMOS Input/Output | Local I2C interface target address select. See Table 8-4. In normal operation, this pin is an input. When the ADDR pin is programmed high, it must be tied to the same 1.8-V power rails where the SN65DSI86 VCCIO 1.8-V power rail is connected. |
| AUXP/N | H8, H9 | LVDS I/O | Auxiliary-channel differential pair |
| DA0P/N | H3, J3 | LVDS Input (HS) CMOS Input/Output (LS) |
MIPI D-PHY channel A data lane 0; data rate up to 1.5 Gbps. |
| DA1P/N | H4, J4 | LVDS Input (HS) CMOS Input (LS) (Failsafe) |
MIPI D-PHY channel a data lane 1; data rate up to 1.5 Gbps. |
| DA2P/N | H6, J6 | LVDS Input (HS) CMOS Input (LS) (Failsafe) |
MIPI D-PHY channel A data lane 2; data rate up to 1.5 Gbps |
| DA3P/N | H7, J7 | LVDS Input (HS) CMOS Input (LS) (Failsafe) |
MIPI D-PHY channel A data lane 3; data rate up to 1.5 Gbps. |
| DACP/N | H5, J5 | LVDS Input (HS) CMOS Input (LS) (Failsafe) |
MIPI D-PHY channel A clock lane; operates up to 750 MHz. Under proper conditions, this clock can be used instead of REFCLK to feed DisplayPort PLL. |
| DB0P/N | C2, C1 | LVDS Input (HS) CMOS Input (LS) (Failsafe) |
MIPI D-PHY channel B data lane 0; data rate up to 1.5 Gbps. |
| DB1P/N | D2, D1 | LVDS Input (HS) CMOS Input (LS) (Failsafe) |
MIPI D-PHY channel B data lane 1; data rate up to 1.5 Gbps. |
| DB2P/N | F2, F1 | LVDS Input (HS) CMOS Input (LS) (Failsafe) |
MIPI D-PHY channel B data lane 2; data rate up to 1.5 Gbps. |
| DB3P/N | G2, G1 | LVDS Input (HS) CMOS Input (LS) (Failsafe) |
MIPI D-PHY channel B data lane 3; data rate up to 1.5 Gbps. |
| DBCP/N | E2, E1 | LVDS Input (HS) CMOS Input (LS) (Failsafe) |
MIPI D-PHY channel B clock lane; operates up to 750 MHz. |
| EN | B1 | CMOS Input (Failsafe) |
Chip enable and reset. Device is reset
(shutdown) when EN is low. Deassertion (low) of EN will cause all internal CSRs and functions to be reset to default state. |
| GND | A8, D8, E4, E5, F4, F5, F6, G8 | Power Supply | Reference ground for digital and analog circuits. |
| GPIO[4:1] | B4, A6, A5, A4 | CMOS Input/Output | General-purpose I/O. See Section 8.3.3 section for details on GPIO functionality. When these pins are set high, tie the pins to the same 1.8-V power rail that the SN65DSI86 VCCIO 1.8-V power rail is connected to. |
| HPD | J8 | CMOS Input with internal
pulldown. (Failsafe) |
HPD input. This input requires a 51-kΩ 1% series resistor. |
| IRQ | A3 | CMOS Output | Interrupt signal |
| ML0P/N | F8, F9 | LVDS output (DP) | DisplayPort lane 0 transmit
differential pair. Supports 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7
Gbps, 3.24 Gbps, 4.32 Gbps, and 5.4 Gbps. All DisplayPort lanes transmit at the same data rate. |
| ML1P/N | E8, E9 | LVDS output (DP) | DisplayPort lane 1 transmit
differential pair. Supports 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7
Gbps, 3.24 Gbps, 4.32 Gbps, and 5.4 Gbps. All DisplayPort lanes transmit at the same data rate. |
| ML2P/N | C8, C9 | LVDS output (DP) | DisplayPort lane 2 transmit
differential pair. Supports 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7
Gbps, 3.24 Gbps, 4.32 Gbps, and 5.4 Gbps. All DisplayPort lanes transmit at the same data rate. |
| ML3P/N | B8, B9 | LVDS output (DP) | DisplayPort lane 3 transmit
differential pair. Supports 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7
Gbps, 3.24 Gbps, 4.32 Gbps, and 5.4 Gbps. All DisplayPort lanes transmit at the same data rate. |
| REFCLK | A7 | Input | Reference clock. Frequency determined
by value programmed in I2C register or value of GPIO[3:1]
latched at rising edge of EN. Supported frequencies are: 12 MHz,
19.2 MHz, 26 MHz, 27 MHz, and 38.4 MHz. This pin must be tied to GND when DACP/N feeds the DisplayPort PLL |
| SCL | H1 | OpenDrain Input/Output (Failsafe) |
Local I2C interface clock. |
| SDA | J1 | OpenDrain Input/Output (Failsafe) |
Local I2C interface bidirectional data signal. |
| TEST1 | B3 | CMOS Input with internal pulldown. |
Used for Texas Instruments internal use only. This pin must be left unconnected or tied to ground. |
| TEST2 | B5 | CMOS Input/Output with internal pulldown |
Used for internal test, HBR2 compliance eye, and symbol error rate measurement pattern. For normal operation, pull down this pin to GND or leave unconnected. See Table 8-15 for information on HBR2 compliance eye and symbol error rate measurement patterns. |
| TEST3 | B7 | NA | Used for Texas Instruments internal use only. This pin must be left unconnected or tied to GND through a 0.1-μF capacitor. |
| VCC | D6, D5, J2, J9 | Power Supply | 1.2-V power supply for digital core |
| VCCA | A9, G9, E6, B2, H2 | Power Supply | 1.2-V power supply for analog
circuits. AVCC and VCC can be applied simultaneously. |
| VCCIO | B6, A2 | Power Supply | 1.8-V power supply for Digital I/O |
| VPLL | D9 | Power Supply | 1.8-V power supply for DisplayPort PLL |