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ZHCSBP5C september 2013 – october 2020 SN65DSI86

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

ZXH|64
- MPBGAK9A

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
MIPI DSI INTERFACE
t_GS	DSI LP glitch suppression pulse width				300	ps
t_HS-SETUP	DSI HS data to clock setup time		0.2			UI
t_HS-HOLD	DSI HS clock to data hold time		0.2			UI
DisplayPort MAIN LINK
F_BR7	Bit rate 7		5.37138	5.4	5.40162	Gbps
F_BR6	Bit rate 6		4.297104	4.32	4.321296	Gbps
F_BR5	Bit rate 5		3.222828	3.24	3.240972	Gbps
F_BR4	Bit rate 4		2.68569	2.7	2.70081	Gbps
F_BR3	Bit rate 3		2.417121	2.43	2.430729	Gbps
F_BR2	Bit rate 2		2.148552	2.16	2.160648	Gbps
F_BR1	Bit rate 1		1.611414	1.62	1.620486	Gbps
UI_BR7	Unit interval for BR7	High limit = +300 ppm. Low limit = –5300 ppm		185		ps
UI_BR6	Unit interval for BR6	High limit = +300 ppm. Low limit = –5300 ppm		231.5		ps
UI_BR5	Unit interval for BR5	High limit = +300 ppm. Low limit = –5300 ppm		308.6		ps
UI_BR4	Unit interval for BR4	High limit = +300 ppm. Low limit = –5300 ppm		370.4		ps
UI_BR3	Unit interval for BR3	High limit = +300 ppm. Low limit = –5300 ppm		411.5		ps
UI_BR2	Unit interval for BR2	High limit = +300 ppm. Low limit = –5300 ppm		463		ps
UI_BR1	Unit interval for BR1	High limit = +300 ppm. Low limit = –5300 ppm		617.3		ps
t_{ERC_L0}	Differential output rise or fall time with DP_ERC set to 0		50	61	80	ps
t_{ERC_L1}	Differential output rise or fall time with DP_ERC set to 1		74	95	115	ps
t_{ERC_L2}	Differential output rise or fall time with DP_ERC set to 2		108	123	146	ps
t_{ERC_L3}	Differential output rise or fall time with DP_ERC set to 3		136	153	168	ps
t_{TX_RISE_FALL} _{_MISMATCH}	Lane intra-pair output skew at TX pins				5%
t_{INTRA_SKEW}	Intra-pair differential skew				20	ps
t_{INTER_SKEW}	Inter-pair differential skew				100	ps
t_{TX_EYE_HBR2}	Minimum TX eye width at TX package pins for HBR2⁽²⁾		0.73			UI_HBR2
t_{TX_EYE_MED_TO} _{_MAX_JIT_HBR2}	Maximum time between the jitter median and maximum deviation from the median at TX package pins for HBR2⁽²⁾				0.135	UI_HBR2
t_{TX_EYE_HBR}	Minimum TX eye width at TX package pins for HBR⁽²⁾		0.72			UI_HBR
t_{TX_EYE_MED_TO} _{_MAX_JIT_HBR}	Maximum time between the jitter median and maximum deviation from the median at TX package pins for HBR⁽²⁾				0.147	UI_HBR
t_{TX_EYE_RBR}	Minimum TX eye width at TX package pins for RBR⁽²⁾		0.82			UI_RBR
t_{TX_EYE_MED_TO} _{_MAX_JIT_RBR}	Maximum time between the jitter median and maximum deviation from the median at TX package pins for RBR⁽²⁾				0.09	UI_RBR
t_{XSSC_AMP}	Link clock down-spreading		0%		0.5%
t_{SSC_FREQ}	Link clock down-spreading frequency		30		33	kHz
DisplayPort AUX INTERFACE
UI_MAN	Manchester transaction unit interval		0.4		0.6	μs
t_{auxjitter_tx}	Cycle-to-cycle jitter time at transmit pins				0.08	UI_MAN
t_{auxjitter_rx}	Cycle-to-cycle jitter time at receive pins				0.04	UI_MAN
REFCLK
f_REFCLK	REFCLK frequency. supported frequencies: 12 MHz, 19.2 MHz, 26 MHz, 27 MHz, 38.4 MHz		12		38.4	MHz
t_RISEFALL	REFCLK rise or fall time	10% to 90%	100 ps		23	ns
t_REFCLK	REFCLK period		26.0417		83.333	ns
t_pj	REFCLK peak-to-peak phase jitter				50	ps
Duty	REFCLK duty cycle		40%	50%	60%

(1) All typical values are at V_CC = 1.2 V and T_A = 25 °C

(2) BR refers to BR1; HBR refers to BR; HBR2 refers to BR7.

Figure 7-1 Power-Up Timing Definitions for DPPLL_CLK_SRC = REFCLK

Figure 7-2 Power-Up Timing Definitions for DPPLL_CLK_SRC = DACP/N

Figure 7-3 SUSPEND Timing Definitions

Figure 7-4 DSI HS Mode Receiver Timing Definitions

Figure 7-5 DSI Receiver Voltage Definitions